Module Definition
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Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.52 100.00 55.56 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.52 100.00 55.56 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_mux_tx_d


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.52 100.00 55.56 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
68.52 100.00 55.56 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_mux_tx_se0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.93 100.00 77.78 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
75.93 100.00 77.78 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_mux_tx_oe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.63 100.00 88.89 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
79.63 100.00 88.89 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_mux_tx_dp


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 100.00 100.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.33 100.00 100.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
i_mux_tx_dn


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT25,T26,T27

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT25,T26,T27
11CoveredT25,T26,T27

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 7602584 7593294 0 0
selKnown1 104 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 7602584 7593294 0 0
T1 23 20 0 0
T2 3 0 0 0
T3 23 20 0 0
T4 952 950 0 0
T5 0 516 0 0
T28 23 20 0 0
T29 69 64 0 0
T30 25 20 0 0
T31 25 20 0 0
T32 25 20 0 0
T33 375 370 0 0
T34 2 20 0 0
T35 2 20 0 0
T36 4 2 0 0
T37 0 2 0 0
T38 0 2 0 0
T39 0 1230 0 0
T40 0 1384 0 0
T41 0 46 0 0
T42 3 0 0 0
T43 2 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 104 0 0 0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT25,T26,T27
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_d.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2485689 2483648 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2485689 2483648 0 0
T1 8 7 0 0
T2 1 0 0 0
T3 8 7 0 0
T28 8 7 0 0
T29 22 21 0 0
T30 8 7 0 0
T31 8 7 0 0
T32 8 7 0 0
T33 124 123 0 0
T34 0 7 0 0
T35 0 7 0 0
T42 1 0 0 0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T28
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT25,T26,T27
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T3,T28

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_se0.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 80202 78616 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 80202 78616 0 0
T4 476 475 0 0
T5 0 258 0 0
T29 2 1 0 0
T30 1 0 0 0
T31 1 0 0 0
T32 1 0 0 0
T33 2 1 0 0
T34 1 0 0 0
T35 1 0 0 0
T36 2 1 0 0
T37 0 1 0 0
T38 0 1 0 0
T39 0 615 0 0
T40 0 692 0 0
T41 0 23 0 0
T43 1 0 0 0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T28
10CoveredT25,T26,T27

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT25,T26,T27
10Not Covered
11CoveredT25,T26,T27

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T3,T28

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_oe.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 80202 78616 0 0
selKnown1 50 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 80202 78616 0 0
T4 476 475 0 0
T5 0 258 0 0
T29 2 1 0 0
T30 1 0 0 0
T31 1 0 0 0
T32 1 0 0 0
T33 2 1 0 0
T34 1 0 0 0
T35 1 0 0 0
T36 2 1 0 0
T37 0 1 0 0
T38 0 1 0 0
T39 0 615 0 0
T40 0 692 0 0
T41 0 23 0 0
T43 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 50 0 0 0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9888.89
Logical9888.89
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT26,T44,T45

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT26,T44,T45
10CoveredT25,T27,T46
11CoveredT26,T44,T45

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dp.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2485689 2483648 0 0
selKnown1 27 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2485689 2483648 0 0
T1 8 7 0 0
T2 1 0 0 0
T3 8 7 0 0
T28 8 7 0 0
T29 22 21 0 0
T30 8 7 0 0
T31 8 7 0 0
T32 8 7 0 0
T33 124 123 0 0
T34 0 7 0 0
T35 0 7 0 0
T42 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 27 0 0 0

Line Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions99100.00
Logical99100.00
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT26,T45,T47

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT26,T45,T47
10CoveredT25,T27,T44
11CoveredT26,T45,T47

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01CoveredT25,T26,T27
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.i_usbdev_iomux.i_mux_tx_dn.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 2470802 2468766 0 0
selKnown1 27 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 2470802 2468766 0 0
T1 7 6 0 0
T2 1 0 0 0
T3 7 6 0 0
T28 7 6 0 0
T29 21 20 0 0
T30 7 6 0 0
T31 7 6 0 0
T32 7 6 0 0
T33 123 122 0 0
T34 0 6 0 0
T35 0 6 0 0
T42 1 0 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 27 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%