Unified Coverage Report :: Module :: usb_fs_tx

Module : usb_fs_tx

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.24	95.11	91.38		58.82	90.91	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_tx.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx	87.24	95.11	91.38		58.82	90.91	100.00

---

Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_tx

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.24	95.11	91.38		58.82	90.91	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.66	95.61	91.38		58.82	92.50	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_usb_fs_nb_pe

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_oe_flop	100.00	100.00				100.00
u_usb_d_flop	100.00	100.00				100.00
u_usb_d_o_flop	100.00	100.00				100.00
u_usb_dn_o_flop	100.00	100.00				100.00
u_usb_dp_o_flop	100.00	100.00				100.00
u_usb_se0_flop	100.00	100.00				100.00
u_usb_se0_o_flop	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usb_fs_tx

	Line No.	Total	Covered	Percent
TOTAL		184	175	95.11
ALWAYS	87	5	5	100.00
CONT_ASSIGN	98	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	102	1	1	100.00
CONT_ASSIGN	103	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	14	14	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	132	1	1	100.00
ALWAYS	140	70	61	87.14
ALWAYS	270	3	3	100.00
CONT_ASSIGN	278	1	1	100.00
CONT_ASSIGN	281	1	1	100.00
ALWAYS	284	5	5	100.00
ALWAYS	300	32	32	100.00
ALWAYS	344	10	10	100.00
ALWAYS	374	19	19	100.00
ALWAYS	416	8	8	100.00
ALWAYS	459	7	7	100.00
CONT_ASSIGN	507	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_tx.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_tx.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
87	1	1
88	1	1
90	1	1
91	1	1
93	1	1
98	1	1
101	1	1
102	1	1
103	1	1
107	1	1
108	1	1
111	1	1
112	1	1
113	1	1
114	1	1
115	1	1
117	1	1
118	1	1
119	1	1
120	1	1
121	1	1
123	1	1
124	1	1
125	1	1
126	1	1
131	1	1
132	1	1
140	1	1
141	1	1
142	1	1
143	1	1
144	1	1
145	1	1
146	1	1
147	1	1
148	1	1
150	1	1
152	1	1
153	0	1
154	0	1
155	1	1
156	1	1
			MISSING_ELSE
161	1	1
162	1	1
163	1	1
164	1	1
165	1	1
			MISSING_ELSE
170	1	1
171	1	1
172	1	1
174	1	1
177	1	1
178	1	1
179	1	1
			MISSING_ELSE
184	1	1
185	1	1
186	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
198	1	1
199	1	1
202	1	1
207	1	1
208	1	1
209	1	1
211	1	1
212	1	1
			MISSING_ELSE
217	1	1
218	1	1
219	1	1
220	1	1
			MISSING_ELSE
226	0	1
227	0	1
228	0	1
229	0	1
230	0	1
231	0	1
232	0	1
			==> MISSING_ELSE
240	1	1
245	1	1
246	1	1
248	1	1
250	1	1
251	1	1
252	1	1
256	1	1
258	1	1
259	1	1
260	1	1
262	1	1
			MISSING_ELSE
270	1	1
271	1	1
273	1	1
278	1	1
281	1	1
284	1	1
286	1	1
287	1	1
			MISSING_ELSE
290	1	1
291	1	1
			MISSING_ELSE
300	1	1
301	1	1
302	1	1
303	1	1
304	1	1
305	1	1
306	1	1
307	1	1
308	1	1
309	1	1
310	1	1
312	1	1
313	1	1
314	1	1
315	1	1
316	1	1
317	1	1
318	1	1
319	1	1
320	1	1
321	1	1
322	1	1
324	1	1
325	1	1
326	1	1
327	1	1
328	1	1
329	1	1
330	1	1
331	1	1
332	1	1
333	1	1
344	1	1
345	1	1
347	1	1
349	1	1
350	1	1
			MISSING_ELSE
355	1	1
356	1	1
			MISSING_ELSE
361	1	1
362	1	1
363	1	1
			MISSING_ELSE
374	1	1
375	1	1
376	1	1
377	1	1
379	1	1
380	1	1
381	1	1
383	1	1
384	1	1
386	1	1
388	1	1
390	1	1
392	1	1
393	1	1
396	1	1
399	1	1
403	1	1
408	1	1
409	1	1
			MISSING_ELSE
			MISSING_ELSE
416	1	1
417	1	1
418	1	1
420	1	1
421	1	1
422	1	1
424	1	1
425	1	1
459	1	1
460	1	1
461	1	1
462	1	1
464	1	1
465	1	1
466	1	1
507	1	1

---

Cond Coverage for Module : usb_fs_tx

	Total	Covered	Percent
Conditions	58	53	91.38
Logical	58	53	91.38
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (pkt_start_i ? pid_i : pid_q)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T28

 LINE       108
 EXPRESSION (bit_history == 6'b111111)
            -------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T33,T4,T36

 LINE       131
 EXPRESSION (bit_strobe_i && (se0_shift_reg_q[1:0] == 2'b1))
             ------1-----    ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T28

 LINE       131
 SUB-EXPRESSION (se0_shift_reg_q[1:0] == 2'b1)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T28

 LINE       171
 EXPRESSION (pid_q[1:0] == 2'b11)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T3,T28
1	Covered	T29,T33,T4

 LINE       226
 EXPRESSION (((!tx_osc_test_mode_i)) && byte_strobe_q)
             -----------1-----------    ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       270
 EXPRESSION (bit_strobe_i && ((!bitstuff)) && ((!pkt_start_i)))
             ------1-----    ------2------    --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T33,T4,T36
1	1	0	Covered	T1,T3,T28
1	1	1	Covered	T1,T2,T3

 LINE       271
 EXPRESSION (bit_count_q == 3'b0)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       281
 EXPRESSION (serial_tx_data ^ crc16_q[15])
             -------1------   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T28
1	0	Covered	T33,T4,T36
1	1	Covered	T1,T3,T28

 LINE       290
 EXPRESSION (bit_strobe_i && data_payload_q && ((!bitstuff_q4)) && ((!pkt_start_i)))
             ------1-----    -------2------    --------3-------    --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T33,T4,T36
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T33,T4,T36
1	1	1	0	Not Covered
1	1	1	1	Covered	T33,T4,T36

 LINE       349
 EXPRESSION (pkt_start_i || test_mode_start)
             -----1-----    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T3,T28

 LINE       362
 EXPRESSION (bit_strobe_i && ((!serial_tx_oe)))
             ------1-----    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T28
1	0	Covered	T1,T3,T28
1	1	Covered	T1,T3,T28

 LINE       383
 EXPRESSION (bit_strobe_i && out_nrzi_en)
             ------1-----    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T28

 LINE       431
 EXPRESSION (link_reset_i ? 1'b0 : oe_d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       440
 EXPRESSION (link_reset_i ? 1'b0 : usb_d_d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       447
 EXPRESSION (link_reset_i ? 1'b0 : usb_se0_d)
             ------1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       461
 EXPRESSION (1'b0 ^ cfg_pinflip_i)
             --1-   ------2------

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T3
-	1	Covered	T51,T52,T53

 LINE       462
 EXPRESSION (1'b1 ^ cfg_pinflip_i)
             --1-   ------2------

-1-	-2-	Status	Tests
-	0	Covered	T1,T2,T3
-	1	Covered	T51,T52,T53

 LINE       465
 EXPRESSION ((cfg_pinflip_i ? ((~usb_d_d)) : usb_d_d) & ((~usb_se0_d)))
             --------------------1-------------------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T4,T36,T5
1	1	Covered	T1,T2,T3

 LINE       465
 SUB-EXPRESSION (cfg_pinflip_i ? ((~usb_d_d)) : usb_d_d)
                 ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T54,T55

 LINE       466
 EXPRESSION ((cfg_pinflip_i ? usb_d_d : ((~usb_d_d))) & ((~usb_se0_d)))
             --------------------1-------------------   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T28
1	1	Covered	T1,T2,T3

 LINE       466
 SUB-EXPRESSION (cfg_pinflip_i ? usb_d_d : ((~usb_d_d)))
                 ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T54,T55

---

FSM Coverage for Module : usb_fs_tx

Summary for FSM :: state_q

	Total	Covered	Percent
States	7	6	85.71	(Not included in score)
Transitions	13	7	53.85
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
Crc161	193	Covered	T29,T33,T4
DataOrCrc160	172	Covered	T29,T33,T4
Eop	174	Covered	T1,T3,T28
Idle	313	Covered	T1,T2,T3
OscTest	153	Not Covered
Pid	162	Covered	T1,T3,T28
Sync	156	Covered	T1,T3,T28

transitions	Line No.	Covered	Tests
Crc161->Eop	208	Covered	T29,T33,T4
Crc161->Idle	313	Not Covered
DataOrCrc160->Crc161	193	Covered	T29,T33,T4
DataOrCrc160->Idle	313	Not Covered
Eop->Idle	313	Covered	T1,T3,T28
Idle->OscTest	153	Not Covered
Idle->Sync	156	Covered	T1,T3,T28
OscTest->Idle	313	Not Covered
Pid->DataOrCrc160	172	Covered	T29,T33,T4
Pid->Eop	174	Covered	T1,T3,T28
Pid->Idle	313	Not Covered
Sync->Idle	313	Not Covered
Sync->Pid	162	Covered	T1,T3,T28

Summary for FSM :: out_state_q

	Total	Covered	Percent
States	3	3	100.00	(Not included in score)
Transitions	4	3	75.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: out_state_q

---

states	Line No.	Covered	Tests
OsIdle	422	Covered	T1,T2,T3
OsTransmit	356	Covered	T1,T3,T28
OsWaitByte	350	Covered	T1,T3,T28

transitions	Line No.	Covered	Tests
OsIdle->OsWaitByte	350	Covered	T1,T3,T28
OsTransmit->OsIdle	422	Covered	T1,T3,T28
OsWaitByte->OsIdle	422	Not Covered
OsWaitByte->OsTransmit	356	Covered	T1,T3,T28

---

Branch Coverage for Module : usb_fs_tx

	Line No.	Total	Covered	Percent
Branches		66	60	90.91
TERNARY	98	2	2	100.00
TERNARY	431	2	2	100.00
TERNARY	440	2	2	100.00
TERNARY	447	2	2	100.00
IF	87	3	3	100.00
IF	111	3	3	100.00
CASE	150	19	14	73.68
IF	240	4	4	100.00
IF	270	2	2	100.00
IF	286	2	2	100.00
IF	290	2	2	100.00
IF	300	3	3	100.00
CASE	347	7	6	85.71
IF	379	8	8	100.00
IF	416	3	3	100.00
IF	459	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_tx.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_tx.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	98	(pkt_start_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	431	(link_reset_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	440	(link_reset_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	447	(link_reset_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	87	if ((!rst_ni))
-2-:	90	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if ((!rst_ni))
-2-:	117	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	150	case (state_q)
-2-:	152	if (tx_osc_test_mode_i)
-3-:	155	if (pkt_start_i)
-4-:	161	if (byte_strobe_q)
-5-:	170	if (byte_strobe_q)
-6-:	171	if ((pid_q[1:0] == 2'b11))
-7-:	184	if (byte_strobe_q)
-8-:	185	if (tx_data_avail_i)
-9-:	207	if (byte_strobe_q)
-10-:	217	if (byte_strobe_q)
-11-:	226	if (((!tx_osc_test_mode_i) && byte_strobe_q))
-12-:	229	if (byte_strobe_q)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	Status	Tests
Idle	1	-	-	-	-	-	-	-	-	-	-	Not Covered
Idle	0	1	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T28
Idle	0	0	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
Sync	-	-	1	-	-	-	-	-	-	-	-	Covered	T1,T3,T28
Sync	-	-	0	-	-	-	-	-	-	-	-	Covered	T1,T3,T28
Pid	-	-	-	1	1	-	-	-	-	-	-	Covered	T29,T33,T4
Pid	-	-	-	1	0	-	-	-	-	-	-	Covered	T1,T3,T28
Pid	-	-	-	0	-	-	-	-	-	-	-	Covered	T1,T3,T28
DataOrCrc160	-	-	-	-	-	1	1	-	-	-	-	Covered	T33,T4,T36
DataOrCrc160	-	-	-	-	-	1	0	-	-	-	-	Covered	T29,T33,T4
DataOrCrc160	-	-	-	-	-	0	-	-	-	-	-	Covered	T29,T33,T4
Crc161	-	-	-	-	-	-	-	1	-	-	-	Covered	T29,T33,T4
Crc161	-	-	-	-	-	-	-	0	-	-	-	Covered	T29,T33,T4
Eop	-	-	-	-	-	-	-	-	1	-	-	Covered	T1,T3,T28
Eop	-	-	-	-	-	-	-	-	0	-	-	Covered	T1,T3,T28
OscTest	-	-	-	-	-	-	-	-	-	1	-	Not Covered
OscTest	-	-	-	-	-	-	-	-	-	0	1	Not Covered
OscTest	-	-	-	-	-	-	-	-	-	0	0	Not Covered
default	-	-	-	-	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	240	if (pkt_start_i)
-2-:	248	if (bit_strobe_i)
-3-:	250	if (bitstuff)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T3,T28
0	1	1	Covered	T33,T4,T36
0	1	0	Covered	T1,T2,T3
0	0	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	270	if (((bit_strobe_i && (!bitstuff)) && (!pkt_start_i)))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	286	if (pkt_start_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T28
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	290	if ((((bit_strobe_i && data_payload_q) && (!bitstuff_q4)) && (!pkt_start_i)))

Branches:

-1-	Status	Tests
1	Covered	T33,T4,T36
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	300	if ((!rst_ni))
-2-:	312	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	347	case (out_state_q)
-2-:	349	if ((pkt_start_i || test_mode_start))
-3-:	355	if (byte_strobe_q)
-4-:	362	if ((bit_strobe_i && (!serial_tx_oe)))

Branches:

-1-	-2-	-3-	-4-	Status	Tests
OsIdle	1	-	-	Covered	T1,T3,T28
OsIdle	0	-	-	Covered	T1,T2,T3
OsWaitByte	-	1	-	Covered	T1,T3,T28
OsWaitByte	-	0	-	Covered	T1,T3,T28
OsTransmit	-	-	1	Covered	T1,T3,T28
OsTransmit	-	-	0	Covered	T1,T3,T28
default	-	-	-	Not Covered

	LineNo.	Expression
-1-:	379	if (pkt_start_i)
-2-:	383	if ((bit_strobe_i && out_nrzi_en))
-3-:	386	if (serial_tx_se0)
-4-:	390	if (dp_eop_q[0])
-5-:	399	if (serial_tx_data)
-6-:	408	if ((!oe_d))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T3,T28
0	1	1	1	-	-	Covered	T1,T3,T28
0	1	1	0	-	-	Covered	T1,T3,T28
0	1	0	-	1	-	Covered	T1,T3,T28
0	1	0	-	0	-	Covered	T1,T3,T28
0	1	-	-	-	1	Covered	T1,T3,T28
0	1	-	-	-	0	Covered	T1,T3,T28
0	0	-	-	-	-	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	416	if ((!rst_ni))
-2-:	420	if (link_reset_i)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	459	if (link_reset_i)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : usb_fs_tx

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutStateValid_A	239813154	239654872	0	0
StateValid_A	239813154	239654872	0	0

OutStateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

StateValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0