Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.39	97.53	79.85	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.39	97.53	79.85	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.47	95.12	77.78			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.39	97.53	79.85	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	86.51	92.59	90.00			76.92

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.42	98.57	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.42	98.57	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.42	98.57	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T95,T4,T96
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T30,T95,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T30,T95,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T30,T95,T4
1	1	0	Not Covered
1	1	1	Covered	T30,T70,T77

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T30,T95,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	239813154	82273811	0	0
DepthKnown_A	239813154	239654872	0	0
RvalidKnown_A	239813154	239654872	0	0
WreadyKnown_A	239813154	239654872	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	239813154	82273811	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	82273811	0	0
T4	105187	104592	0	0
T5	0	113237	0	0
T6	0	562412	0	0
T30	7003	575	0	0
T31	7520	0	0	0
T32	8551	0	0	0
T33	11698	0	0	0
T34	6970	0	0	0
T35	9146	0	0	0
T42	7996	0	0	0
T43	9104	0	0	0
T70	0	560	0	0
T76	0	555	0	0
T77	0	571	0	0
T95	8027	1787	0	0
T96	0	738	0	0
T98	0	631259	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	82273811	0	0
T4	105187	104592	0	0
T5	0	113237	0	0
T6	0	562412	0	0
T30	7003	575	0	0
T31	7520	0	0	0
T32	8551	0	0	0
T33	11698	0	0	0
T34	6970	0	0	0
T35	9146	0	0	0
T42	7996	0	0	0
T43	9104	0	0	0
T70	0	560	0	0
T76	0	555	0	0
T77	0	571	0	0
T95	8027	1787	0	0
T96	0	738	0	0
T98	0	631259	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T95,T4,T96
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T3,T28

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T28

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T3,T28
1	1	0	Not Covered
1	1	1	Covered	T1,T29,T32

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T28
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	239813154	106903364	0	0
DepthKnown_A	239813154	239654872	0	0
RvalidKnown_A	239813154	239654872	0	0
WreadyKnown_A	239813154	239654872	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	239813154	106903364	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	106903364	0	0
T1	8008	750	0	0
T2	7277	0	0	0
T3	7402	1669	0	0
T28	8375	2468	0	0
T29	7771	310	0	0
T30	7003	0	0	0
T31	7520	1640	0	0
T32	8551	2202	0	0
T33	11698	2077	0	0
T34	0	311	0	0
T42	7996	895	0	0
T95	0	1425	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	106903364	0	0
T1	8008	750	0	0
T2	7277	0	0	0
T3	7402	1669	0	0
T28	8375	2468	0	0
T29	7771	310	0	0
T30	7003	0	0	0
T31	7520	1640	0	0
T32	8551	2202	0	0
T33	11698	2077	0	0
T34	0	311	0	0
T42	7996	895	0	0
T95	0	1425	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T29,T30

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T29,T30

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T29,T30
1	1	0	Not Covered
1	1	1	Covered	T1,T32,T34

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T29,T30
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T29,T30

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T29,T30
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	239813154	2890120	0	0
DepthKnown_A	239813154	239654872	0	0
RvalidKnown_A	239813154	239654872	0	0
WreadyKnown_A	239813154	239654872	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	239813154	2890120	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	2890120	0	0
T1	8008	101	0	0
T2	7277	0	0	0
T3	7402	0	0	0
T4	0	7003	0	0
T5	0	944	0	0
T28	8375	0	0	0
T29	7771	1318	0	0
T30	7003	769	0	0
T31	7520	0	0	0
T32	8551	92	0	0
T33	11698	3103	0	0
T34	0	112	0	0
T36	0	3231	0	0
T42	7996	0	0	0
T50	0	86	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	2890120	0	0
T1	8008	101	0	0
T2	7277	0	0	0
T3	7402	0	0	0
T4	0	7003	0	0
T5	0	944	0	0
T28	8375	0	0	0
T29	7771	1318	0	0
T30	7003	769	0	0
T31	7520	0	0	0
T32	8551	92	0	0
T33	11698	3103	0	0
T34	0	112	0	0
T36	0	3231	0	0
T42	7996	0	0	0
T50	0	86	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	241576707	18694925	0	0
DepthKnown_A	241576707	241360327	0	0
RvalidKnown_A	241576707	241360327	0	0
WreadyKnown_A	241576707	241360327	0	0
gen_passthru_fifo.paramCheckPass	2216	2216	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	18694925	0	0
T1	8008	17	0	0
T2	7277	11	0	0
T3	7402	10	0	0
T28	8375	10	0	0
T29	7771	12	0	0
T30	7003	13	0	0
T31	7520	10	0	0
T32	8551	28	0	0
T33	11698	12	0	0
T42	7996	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2216	2216	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T42	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	241576707	27795172	0	0
DepthKnown_A	241576707	241360327	0	0
RvalidKnown_A	241576707	241360327	0	0
WreadyKnown_A	241576707	241360327	0	0
gen_passthru_fifo.paramCheckPass	2216	2216	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	27795172	0	0
T1	8008	17	0	0
T2	7277	46	0	0
T3	7402	10	0	0
T28	8375	10	0	0
T29	7771	45	0	0
T30	7003	13	0	0
T31	7520	10	0	0
T32	8551	28	0	0
T33	11698	12	0	0
T42	7996	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2216	2216	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T42	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	241576707	373496	0	0
DepthKnown_A	241576707	241360327	0	0
RvalidKnown_A	241576707	241360327	0	0
WreadyKnown_A	241576707	241360327	0	0
gen_passthru_fifo.paramCheckPass	2216	2216	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	373496	0	0
T1	8008	4	0	0
T2	7277	0	0	0
T3	7402	0	0	0
T28	8375	0	0	0
T29	7771	0	0	0
T30	7003	0	0	0
T31	7520	0	0	0
T32	8551	15	0	0
T33	11698	0	0	0
T38	0	11	0	0
T39	0	6451	0	0
T40	0	7356	0	0
T41	0	133	0	0
T42	7996	0	0	0
T50	0	1	0	0
T58	0	117	0	0
T94	0	2	0	0
T97	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2216	2216	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T42	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	241576707	640285	0	0
DepthKnown_A	241576707	241360327	0	0
RvalidKnown_A	241576707	241360327	0	0
WreadyKnown_A	241576707	241360327	0	0
gen_passthru_fifo.paramCheckPass	2216	2216	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	640285	0	0
T1	8008	4	0	0
T2	7277	0	0	0
T3	7402	0	0	0
T28	8375	0	0	0
T29	7771	0	0	0
T30	7003	0	0	0
T31	7520	0	0	0
T32	8551	15	0	0
T33	11698	0	0	0
T38	0	11	0	0
T39	0	6451	0	0
T40	0	7356	0	0
T41	0	623	0	0
T42	7996	0	0	0
T50	0	5	0	0
T58	0	117	0	0
T94	0	2	0	0
T97	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2216	2216	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T42	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	241576707	18259142	0	0
DepthKnown_A	241576707	241360327	0	0
RvalidKnown_A	241576707	241360327	0	0
WreadyKnown_A	241576707	241360327	0	0
gen_passthru_fifo.paramCheckPass	2216	2216	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	18259142	0	0
T1	8008	13	0	0
T2	7277	11	0	0
T3	7402	10	0	0
T28	8375	10	0	0
T29	7771	12	0	0
T30	7003	13	0	0
T31	7520	10	0	0
T32	8551	13	0	0
T33	11698	12	0	0
T42	7996	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2216	2216	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T42	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	241576707	27154887	0	0
DepthKnown_A	241576707	241360327	0	0
RvalidKnown_A	241576707	241360327	0	0
WreadyKnown_A	241576707	241360327	0	0
gen_passthru_fifo.paramCheckPass	2216	2216	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	27154887	0	0
T1	8008	13	0	0
T2	7277	46	0	0
T3	7402	10	0	0
T28	8375	10	0	0
T29	7771	45	0	0
T30	7003	13	0	0
T31	7520	10	0	0
T32	8551	13	0	0
T33	11698	12	0	0
T42	7996	11	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	241576707	241360327	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2216	2216	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T42	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T32,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T32,T50

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T32,T50

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T32,T50,T94
1	1	0	Not Covered
1	1	1	Covered	T1,T32,T50

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T32,T50
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T32,T50

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T32,T50
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	239813154	576775	0	0
DepthKnown_A	239813154	239654872	0	0
RvalidKnown_A	239813154	239654872	0	0
WreadyKnown_A	239813154	239654872	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	239813154	576775	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	576775	0	0
T1	8008	4	0	0
T2	7277	0	0	0
T3	7402	0	0	0
T28	8375	0	0	0
T29	7771	0	0	0
T30	7003	0	0	0
T31	7520	0	0	0
T32	8551	15	0	0
T33	11698	0	0	0
T38	0	11	0	0
T39	0	6451	0	0
T40	0	7356	0	0
T41	0	623	0	0
T42	7996	0	0	0
T50	0	5	0	0
T58	0	117	0	0
T94	0	2	0	0
T97	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	576775	0	0
T1	8008	4	0	0
T2	7277	0	0	0
T3	7402	0	0	0
T28	8375	0	0	0
T29	7771	0	0	0
T30	7003	0	0	0
T31	7520	0	0	0
T32	8551	15	0	0
T33	11698	0	0	0
T38	0	11	0	0
T39	0	6451	0	0
T40	0	7356	0	0
T41	0	623	0	0
T42	7996	0	0	0
T50	0	5	0	0
T58	0	117	0	0
T94	0	2	0	0
T97	0	2	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T32,T50
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T32,T50

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T32,T50

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T32,T50

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T32,T50
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T32,T50

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T32,T50
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	239813154	207015	0	0
DepthKnown_A	239813154	239654872	0	0
RvalidKnown_A	239813154	239654872	0	0
WreadyKnown_A	239813154	239654872	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	239813154	207015	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	207015	0	0
T1	8008	4	0	0
T2	7277	0	0	0
T3	7402	0	0	0
T28	8375	0	0	0
T29	7771	0	0	0
T30	7003	0	0	0
T31	7520	0	0	0
T32	8551	15	0	0
T33	11698	0	0	0
T38	0	11	0	0
T39	0	3862	0	0
T40	0	4505	0	0
T41	0	133	0	0
T42	7996	0	0	0
T50	0	1	0	0
T58	0	117	0	0
T94	0	2	0	0
T97	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	207015	0	0
T1	8008	4	0	0
T2	7277	0	0	0
T3	7402	0	0	0
T28	8375	0	0	0
T29	7771	0	0	0
T30	7003	0	0	0
T31	7520	0	0	0
T32	8551	15	0	0
T33	11698	0	0	0
T38	0	11	0	0
T39	0	3862	0	0
T40	0	4505	0	0
T41	0	133	0	0
T42	7996	0	0	0
T50	0	1	0	0
T58	0	117	0	0
T94	0	2	0	0
T97	0	2	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T50,T41,T56
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T32,T50

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T32,T50

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T32,T50,T94
1	1	0	Not Covered
1	1	1	Covered	T1,T32,T50

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T32,T50

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T32,T50

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T50,T41,T56
1	0	Covered	T1,T32,T50
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T32,T50
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T32,T50
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T32,T50

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T32,T50
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	239813154	356429	0	0
DepthKnown_A	239813154	239654872	0	0
RvalidKnown_A	239813154	239654872	0	0
WreadyKnown_A	239813154	239654872	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	239813154	356429	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	356429	0	0
T1	8008	4	0	0
T2	7277	0	0	0
T3	7402	0	0	0
T28	8375	0	0	0
T29	7771	0	0	0
T30	7003	0	0	0
T31	7520	0	0	0
T32	8551	15	0	0
T33	11698	0	0	0
T38	0	11	0	0
T39	0	3862	0	0
T40	0	4505	0	0
T41	0	623	0	0
T42	7996	0	0	0
T50	0	5	0	0
T58	0	117	0	0
T94	0	2	0	0
T97	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	239654872	0	0
T1	8008	7942	0	0
T2	7277	7213	0	0
T3	7402	7323	0	0
T28	8375	8324	0	0
T29	7771	7671	0	0
T30	7003	6951	0	0
T31	7520	7441	0	0
T32	8551	8477	0	0
T33	11698	11630	0	0
T42	7996	7929	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	239813154	356429	0	0
T1	8008	4	0	0
T2	7277	0	0	0
T3	7402	0	0	0
T28	8375	0	0	0
T29	7771	0	0	0
T30	7003	0	0	0
T31	7520	0	0	0
T32	8551	15	0	0
T33	11698	0	0	0
T38	0	11	0	0
T39	0	3862	0	0
T40	0	4505	0	0
T41	0	623	0	0
T42	7996	0	0	0
T50	0	5	0	0
T58	0	117	0	0
T94	0	2	0	0
T97	0	2	0	0