Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	55857	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	59285	1		T1	15		T2	37		T3	951

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	71053	1		T1	11		T2	186		T3	1875
values[0x0]	21497	1		T1	8		T2	23		T3	25
values[0x1]	22592	1		T1	3		T2	28		T3	26

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	38811	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	76331	1		T1	16		T2	98		T3	1156

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	374	1		T3	3		T8	2		T11	1
valid_sources[0x01]	404	1		T11	2		T25	12		T6	1
valid_sources[0x02]	318	1		T3	4		T11	1		T10	2
valid_sources[0x03]	432	1		T2	2		T3	7		T11	3
valid_sources[0x04]	427	1		T3	3		T8	1		T10	6
valid_sources[0x05]	391	1		T2	4		T3	16		T9	2
valid_sources[0x06]	475	1		T11	1		T25	1		T4	23
valid_sources[0x07]	377	1		T3	8		T11	2		T9	1
valid_sources[0x08]	341	1		T2	2		T3	9		T8	1
valid_sources[0x09]	331	1		T3	4		T8	1		T11	2
valid_sources[0x0a]	353	1		T2	1		T3	12		T8	2
valid_sources[0x0b]	458	1		T2	2		T3	4		T11	1
valid_sources[0x0c]	359	1		T2	1		T3	7		T10	1
valid_sources[0x0d]	481	1		T2	1		T3	3		T25	18
valid_sources[0x0e]	318	1		T2	1		T3	6		T9	1
valid_sources[0x0f]	646	1		T3	14		T8	1		T10	3
valid_sources[0x10]	372	1		T1	5		T3	6		T8	1
valid_sources[0x11]	479	1		T2	1		T3	4		T8	2
valid_sources[0x12]	315	1		T3	2		T11	1		T25	12
valid_sources[0x13]	422	1		T2	1		T3	8		T11	1
valid_sources[0x14]	275	1		T3	11		T11	1		T10	6
valid_sources[0x15]	422	1		T2	1		T3	21		T11	1
valid_sources[0x16]	396	1		T2	3		T3	4		T11	1
valid_sources[0x17]	347	1		T3	5		T11	3		T25	18
valid_sources[0x18]	384	1		T3	7		T11	1		T10	1
valid_sources[0x19]	461	1		T2	3		T3	3		T11	1
valid_sources[0x1a]	460	1		T3	8		T25	2		T5	13
valid_sources[0x1b]	303	1		T3	4		T8	4		T11	1
valid_sources[0x1c]	431	1		T2	1		T3	6		T8	1
valid_sources[0x1d]	482	1		T3	14		T6	1		T18	2
valid_sources[0x1e]	429	1		T2	5		T3	9		T8	1
valid_sources[0x1f]	314	1		T2	1		T3	7		T11	2
valid_sources[0x20]	541	1		T2	2		T3	6		T8	3
valid_sources[0x21]	395	1		T3	18		T8	1		T25	1
valid_sources[0x22]	398	1		T3	9		T8	2		T11	3
valid_sources[0x23]	492	1		T2	1		T3	3		T25	23
valid_sources[0x24]	525	1		T2	1		T3	9		T8	1
valid_sources[0x25]	442	1		T3	11		T8	1		T10	1
valid_sources[0x26]	458	1		T3	4		T25	22		T19	48
valid_sources[0x27]	601	1		T2	1		T3	8		T10	3
valid_sources[0x28]	298	1		T2	1		T3	1		T11	1
valid_sources[0x29]	361	1		T2	3		T3	5		T11	1
valid_sources[0x2a]	521	1		T2	2		T3	7		T8	1
valid_sources[0x2b]	603	1		T3	2		T11	3		T9	1
valid_sources[0x2c]	480	1		T3	3		T8	1		T10	1
valid_sources[0x2d]	483	1		T2	2		T3	4		T11	3
valid_sources[0x2e]	702	1		T2	1		T3	18		T25	5
valid_sources[0x2f]	377	1		T3	11		T10	1		T25	19
valid_sources[0x30]	254	1		T3	7		T10	1		T25	4
valid_sources[0x31]	329	1		T3	6		T11	2		T25	12
valid_sources[0x32]	587	1		T3	5		T11	3		T25	21
valid_sources[0x33]	342	1		T3	4		T8	1		T25	8
valid_sources[0x34]	409	1		T3	13		T11	1		T10	2
valid_sources[0x35]	355	1		T2	1		T3	6		T8	1
valid_sources[0x36]	347	1		T3	7		T11	3		T10	3
valid_sources[0x37]	361	1		T2	2		T3	9		T8	1
valid_sources[0x38]	331	1		T2	2		T3	5		T11	2
valid_sources[0x39]	422	1		T2	2		T3	14		T10	1
valid_sources[0x3a]	328	1		T3	19		T9	1		T10	2
valid_sources[0x3b]	430	1		T3	14		T11	1		T25	6
valid_sources[0x3c]	546	1		T3	5		T8	2		T11	1
valid_sources[0x3d]	260	1		T3	12		T8	1		T11	1
valid_sources[0x3e]	486	1		T2	1		T3	14		T8	2
valid_sources[0x3f]	598	1		T8	1		T11	1		T10	2
valid_sources[0x40]	287	1		T3	4		T8	1		T11	1
valid_sources[0x41]	396	1		T2	1		T3	13		T8	1
valid_sources[0x42]	413	1		T3	1		T11	1		T25	6
valid_sources[0x43]	553	1		T3	11		T8	1		T25	18
valid_sources[0x44]	342	1		T2	2		T3	5		T11	2
valid_sources[0x45]	239	1		T1	3		T3	15		T8	2
valid_sources[0x46]	422	1		T3	2		T8	2		T10	3
valid_sources[0x47]	339	1		T3	9		T25	7		T18	4
valid_sources[0x48]	414	1		T2	2		T3	3		T11	3
valid_sources[0x49]	373	1		T3	2		T10	3		T25	5
valid_sources[0x4a]	669	1		T2	1		T3	8		T11	4
valid_sources[0x4b]	327	1		T2	3		T3	14		T8	1
valid_sources[0x4c]	462	1		T3	5		T18	1		T20	1
valid_sources[0x4d]	535	1		T3	11		T11	1		T10	1
valid_sources[0x4e]	388	1		T2	4		T3	4		T11	1
valid_sources[0x4f]	606	1		T3	4		T7	40		T8	1
valid_sources[0x50]	544	1		T2	5		T3	24		T11	2
valid_sources[0x51]	333	1		T3	5		T8	2		T20	4
valid_sources[0x52]	1137	1		T2	2		T3	16		T8	2
valid_sources[0x53]	381	1		T2	2		T3	4		T8	2
valid_sources[0x54]	559	1		T3	14		T11	2		T10	1
valid_sources[0x55]	391	1		T2	2		T3	1		T25	5
valid_sources[0x56]	441	1		T3	4		T8	4		T11	1
valid_sources[0x57]	466	1		T3	16		T5	4		T6	5
valid_sources[0x58]	487	1		T3	7		T8	2		T11	1
valid_sources[0x59]	314	1		T2	2		T3	20		T11	3
valid_sources[0x5a]	524	1		T3	3		T11	2		T25	13
valid_sources[0x5b]	340	1		T2	1		T3	15		T8	2
valid_sources[0x5c]	284	1		T3	3		T8	3		T11	3
valid_sources[0x5d]	406	1		T2	2		T3	8		T10	1
valid_sources[0x5e]	400	1		T3	6		T8	8		T11	2
valid_sources[0x5f]	276	1		T2	1		T3	9		T9	4
valid_sources[0x60]	430	1		T1	1		T2	4		T3	13
valid_sources[0x61]	588	1		T2	5		T3	7		T11	3
valid_sources[0x62]	307	1		T2	4		T3	7		T11	4
valid_sources[0x63]	382	1		T3	3		T8	5		T11	3
valid_sources[0x64]	559	1		T11	1		T25	1		T5	3
valid_sources[0x65]	373	1		T2	1		T3	13		T11	2
valid_sources[0x66]	442	1		T11	2		T6	1		T18	2
valid_sources[0x67]	394	1		T3	10		T11	1		T25	3
valid_sources[0x68]	496	1		T3	5		T11	2		T25	2
valid_sources[0x69]	577	1		T2	1		T3	12		T25	2
valid_sources[0x6a]	514	1		T2	3		T3	18		T8	2
valid_sources[0x6b]	462	1		T1	3		T3	6		T8	1
valid_sources[0x6c]	334	1		T2	3		T3	2		T8	1
valid_sources[0x6d]	438	1		T2	1		T3	10		T8	2
valid_sources[0x6e]	386	1		T2	1		T3	12		T11	1
valid_sources[0x6f]	668	1		T2	1		T3	6		T11	2
valid_sources[0x70]	539	1		T3	2		T8	2		T11	2
valid_sources[0x71]	376	1		T2	2		T3	11		T11	1
valid_sources[0x72]	532	1		T2	1		T3	4		T10	1
valid_sources[0x73]	278	1		T3	10		T11	3		T25	28
valid_sources[0x74]	338	1		T2	1		T3	13		T11	1
valid_sources[0x75]	436	1		T3	7		T8	1		T11	1
valid_sources[0x76]	491	1		T3	8		T8	1		T11	1
valid_sources[0x77]	464	1		T1	1		T2	2		T3	7
valid_sources[0x78]	313	1		T2	1		T3	12		T10	1
valid_sources[0x79]	576	1		T3	10		T11	2		T25	6
valid_sources[0x7a]	457	1		T3	13		T10	1		T25	4
valid_sources[0x7b]	300	1		T2	1		T3	5		T8	1
valid_sources[0x7c]	685	1		T3	3		T25	9		T4	16
valid_sources[0x7d]	353	1		T3	8		T8	1		T11	1
valid_sources[0x7e]	655	1		T1	1		T2	2		T3	13
valid_sources[0x7f]	463	1		T2	1		T3	3		T11	1
valid_sources[0x80]	383	1		T3	5		T11	1		T10	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24628

1

T1

5

T2

15

T3

924

values[0x0]

all_enables

biggest_size

18325

1

T1

8

T2

15

T3

14

values[0x1]

all_enables

biggest_size

16332

1

T1

2

T2

7

T3

13