Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	70759	1		T1	7		T2	200		T3	975
full_word	60348	1		T1	15		T2	37		T3	951

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	130837	1		T1	22		T2	237		T3	1926
auto[TlIntgErrCmd]	87	1		T4	5		T57	6		T29	1
auto[TlIntgErrData]	95	1		T4	3		T57	2		T29	3
auto[TlIntgErrBoth]	88	1		T4	2		T57	2		T29	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	73001	1		T1	11		T2	186		T3	1875
auto[1]	58106	1		T1	11		T2	51		T3	51

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	48067	1		T1	6		T2	171		T3	951
auto[TlIntgErrNone]	partial	auto[1]	22445	1		T1	1		T2	29		T3	24
auto[TlIntgErrNone]	full_word	auto[0]	24813	1		T1	5		T2	15		T3	924
auto[TlIntgErrNone]	full_word	auto[1]	35512	1		T1	10		T2	22		T3	27
auto[TlIntgErrCmd]	partial	auto[0]	31	1		T4	2		T57	2		T29	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T4	3		T57	3		T82	1
auto[TlIntgErrCmd]	full_word	auto[0]	4	1		T57	1		T87	1		T88	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T84	1		T86	1		T47	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T4	1		T57	2		T82	4
auto[TlIntgErrData]	partial	auto[1]	46	1		T4	2		T29	3		T82	4
auto[TlIntgErrData]	full_word	auto[0]	5	1		T55	1		T85	1		T88	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T89	1		T90	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	33	1		T57	1		T29	1		T83	4
auto[TlIntgErrBoth]	partial	auto[1]	47	1		T4	2		T57	1		T29	4
auto[TlIntgErrBoth]	full_word	auto[0]	6	1		T55	1		T59	1		T47	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T29	1		T82	1		-	-