Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
23.07	0.00	0.00	92.27		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1845576	12239	0	0
ep_in_enable_rd_A	1845576	2678	0	0
ep_out_enable_rd_A	1845576	2688	0	0
in_iso_rd_A	1845576	2839	0	0
intr_enable_rd_A	1845576	3425	0	0
out_iso_rd_A	1845576	2549	0	0
phy_config_rd_A	1845576	1855	0	0
phy_pins_drive_rd_A	1845576	2327	0	0
rxenable_setup_rd_A	1845576	2293	0	0
set_nak_out_rd_A	1845576	2745	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	12239	0	0
T4	24143	1	0	0
T5	10136	0	0	0
T6	4120	0	0	0
T8	4641	520	0	0
T9	3198	0	0	0
T10	2912	304	0	0
T11	3749	0	0	0
T16	2353	0	0	0
T17	13195	0	0	0
T19	0	19	0	0
T20	0	586	0	0
T21	0	642	0	0
T22	0	341	0	0
T24	0	11	0	0
T25	18064	0	0	0
T29	0	3	0	0
T57	0	3	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	2678	0	0
T2	5242	47	0	0
T3	17365	213	0	0
T5	0	38	0	0
T7	2837	0	0	0
T8	4641	0	0	0
T9	3198	0	0	0
T10	2912	0	0	0
T11	3749	45	0	0
T16	2353	0	0	0
T17	13195	0	0	0
T25	18064	236	0	0
T26	0	17	0	0
T44	0	14	0	0
T63	0	22	0	0
T64	0	7	0	0
T65	0	10	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	2688	0	0
T2	5242	51	0	0
T3	17365	177	0	0
T5	0	50	0	0
T7	2837	0	0	0
T8	4641	0	0	0
T9	3198	0	0	0
T10	2912	0	0	0
T11	3749	81	0	0
T16	2353	0	0	0
T17	13195	0	0	0
T25	18064	190	0	0
T26	0	116	0	0
T44	0	5	0	0
T63	0	5	0	0
T64	0	54	0	0
T65	0	36	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	2839	0	0
T2	5242	55	0	0
T3	17365	180	0	0
T5	0	57	0	0
T7	2837	0	0	0
T8	4641	0	0	0
T9	3198	0	0	0
T10	2912	0	0	0
T11	3749	91	0	0
T16	2353	0	0	0
T17	13195	0	0	0
T25	18064	219	0	0
T26	0	67	0	0
T55	0	83	0	0
T63	0	21	0	0
T64	0	41	0	0
T65	0	33	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	3425	0	0
T3	17365	173	0	0
T4	24143	0	0	0
T5	0	10	0	0
T7	2837	0	0	0
T8	4641	0	0	0
T9	3198	0	0	0
T10	2912	0	0	0
T11	3749	138	0	0
T16	2353	0	0	0
T17	13195	0	0	0
T25	18064	173	0	0
T26	0	80	0	0
T44	0	23	0	0
T63	0	36	0	0
T64	0	82	0	0
T66	0	8	0	0
T67	0	13	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	2549	0	0
T2	5242	48	0	0
T3	17365	193	0	0
T5	0	8	0	0
T7	2837	0	0	0
T8	4641	0	0	0
T9	3198	0	0	0
T10	2912	0	0	0
T11	3749	51	0	0
T16	2353	0	0	0
T17	13195	0	0	0
T25	18064	205	0	0
T26	0	7	0	0
T44	0	10	0	0
T63	0	11	0	0
T64	0	4	0	0
T65	0	13	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1855	0	0
T2	5242	9	0	0
T3	17365	189	0	0
T5	0	33	0	0
T7	2837	0	0	0
T8	4641	0	0	0
T9	3198	0	0	0
T10	2912	0	0	0
T11	3749	53	0	0
T16	2353	0	0	0
T17	13195	0	0	0
T25	18064	180	0	0
T26	0	10	0	0
T44	0	31	0	0
T55	0	77	0	0
T63	0	60	0	0
T65	0	50	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	2327	0	0
T2	5242	34	0	0
T3	17365	248	0	0
T5	0	30	0	0
T7	2837	0	0	0
T8	4641	0	0	0
T9	3198	0	0	0
T10	2912	0	0	0
T11	3749	4	0	0
T16	2353	0	0	0
T17	13195	0	0	0
T25	18064	198	0	0
T26	0	44	0	0
T44	0	25	0	0
T63	0	7	0	0
T64	0	42	0	0
T65	0	16	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	2293	0	0
T3	17365	181	0	0
T4	24143	0	0	0
T5	0	31	0	0
T7	2837	0	0	0
T8	4641	0	0	0
T9	3198	0	0	0
T10	2912	0	0	0
T11	3749	71	0	0
T16	2353	0	0	0
T17	13195	0	0	0
T25	18064	171	0	0
T26	0	57	0	0
T44	0	42	0	0
T55	0	102	0	0
T63	0	19	0	0
T64	0	40	0	0
T65	0	31	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	2745	0	0
T2	5242	7	0	0
T3	17365	198	0	0
T5	0	47	0	0
T7	2837	0	0	0
T8	4641	0	0	0
T9	3198	0	0	0
T10	2912	0	0	0
T11	3749	80	0	0
T16	2353	0	0	0
T17	13195	0	0	0
T25	18064	191	0	0
T26	0	14	0	0
T44	0	32	0	0
T63	0	38	0	0
T64	0	47	0	0
T65	0	31	0	0