Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
23.07	0.00	0.00	92.27		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00			0.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
23.07	0.00	0.00	92.27		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00			0.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
23.07	0.00	0.00	92.27		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00			0.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00			0.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00			0.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	0.00	0.00	0.00			0.00

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	69	4	0	0.00
CONT_ASSIGN	81	1	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	100	1	0	0.00
CONT_ASSIGN	101	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
ALWAYS	123	2	0	0.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	140	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	0	1
70	0	1
71	0	1
72	0	1
			==> MISSING_ELSE
81	0	1
82	0	1
100	0	1
101	0	1
120	0	1
123	0	1
124	0	1
			==> MISSING_ELSE
133	0	1
134	0	1
140	0	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	0	0.00
Logical	14	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	0	0.00
IF	69	3	0	0.00
IF	123	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	69	4	0	0.00
CONT_ASSIGN	81	1	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	100	1	0	0.00
CONT_ASSIGN	101	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
ALWAYS	123	2	0	0.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	140	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	0	1
70	0	1
71	0	1
72	0	1
			==> MISSING_ELSE
81	0	1
82	0	1
100	0	1
101	0	1
120	0	1
123	0	1
124	0	1
			==> MISSING_ELSE
133	0	1
134	0	1
140	0	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	0	0.00
Logical	14	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	0	0.00
IF	69	3	0	0.00
IF	123	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	0	0.00
ALWAYS	69	4	0	0.00
CONT_ASSIGN	81	1	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	100	1	0	0.00
CONT_ASSIGN	101	1	0	0.00
CONT_ASSIGN	120	1	0	0.00
ALWAYS	123	2	0	0.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	138	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	0	1
70	0	1
71	0	1
72	0	1
			==> MISSING_ELSE
81	0	1
82	0	1
100	0	1
101	0	1
120	0	1
123	0	1
124	0	1
			==> MISSING_ELSE
133	0	1
134	0	1
138	0	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	0	0.00
Logical	16	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	0	0.00
TERNARY	138	2	0	0.00
IF	69	3	0	0.00
IF	123	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1845576	330824	0	0
DepthKnown_A	1845576	1794784	0	0
RvalidKnown_A	1845576	1794784	0	0
WreadyKnown_A	1845576	1794784	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	330824	0	0
T1	1931	22	0	0
T2	5242	662	0	0
T3	17365	4924	0	0
T7	2837	40	0	0
T8	4641	1708	0	0
T9	3198	40	0	0
T10	2912	1098	0	0
T11	3749	849	0	0
T16	2353	40	0	0
T17	13195	1538	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1845576	256567	0	0
DepthKnown_A	1845576	1794784	0	0
RvalidKnown_A	1845576	1794784	0	0
WreadyKnown_A	1845576	1794784	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	256567	0	0
T1	1931	22	0	0
T2	5242	769	0	0
T3	17365	9727	0	0
T7	2837	40	0	0
T8	4641	861	0	0
T9	3198	40	0	0
T10	2912	555	0	0
T11	3749	1540	0	0
T16	2353	40	0	0
T17	13195	1538	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1845576	34921	0	0
DepthKnown_A	1845576	1794784	0	0
RvalidKnown_A	1845576	1794784	0	0
WreadyKnown_A	1845576	1794784	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	34921	0	0
T4	24143	0	0	0
T5	10136	0	0	0
T6	4120	0	0	0
T8	4641	190	0	0
T9	3198	0	0	0
T10	2912	258	0	0
T11	3749	0	0	0
T16	2353	0	0	0
T17	13195	1535	0	0
T18	0	1091	0	0
T19	0	918	0	0
T20	0	493	0	0
T21	0	397	0	0
T22	0	226	0	0
T23	0	1535	0	0
T24	0	226	0	0
T25	18064	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1845576	49238	0	0
DepthKnown_A	1845576	1794784	0	0
RvalidKnown_A	1845576	1794784	0	0
WreadyKnown_A	1845576	1794784	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	49238	0	0
T4	24143	0	0	0
T5	10136	0	0	0
T6	4120	0	0	0
T8	4641	166	0	0
T9	3198	0	0	0
T10	2912	193	0	0
T11	3749	0	0	0
T16	2353	0	0	0
T17	13195	1535	0	0
T18	0	1016	0	0
T19	0	498	0	0
T20	0	373	0	0
T21	0	337	0	0
T22	0	221	0	0
T23	0	1535	0	0
T24	0	207	0	0
T25	18064	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1845576	286036	0	0
DepthKnown_A	1845576	1794784	0	0
RvalidKnown_A	1845576	1794784	0	0
WreadyKnown_A	1845576	1794784	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	286036	0	0
T1	1931	22	0	0
T2	5242	662	0	0
T3	17365	4924	0	0
T7	2837	40	0	0
T8	4641	1242	0	0
T9	3198	40	0	0
T10	2912	599	0	0
T11	3749	849	0	0
T16	2353	40	0	0
T17	13195	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	1845576	207329	0	0
DepthKnown_A	1845576	1794784	0	0
RvalidKnown_A	1845576	1794784	0	0
WreadyKnown_A	1845576	1794784	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	207329	0	0
T1	1931	22	0	0
T2	5242	769	0	0
T3	17365	9727	0	0
T7	2837	40	0	0
T8	4641	695	0	0
T9	3198	40	0	0
T10	2912	362	0	0
T11	3749	1540	0	0
T16	2353	40	0	0
T17	13195	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1845576	1794784	0	0
T1	1931	1877	0	0
T2	5242	5158	0	0
T3	17365	17298	0	0
T7	2837	2759	0	0
T8	4641	4587	0	0
T9	3198	3142	0	0
T10	2912	2853	0	0
T11	3749	3699	0	0
T16	2353	2287	0	0
T17	13195	13138	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	0	0.00
ALWAYS	69	4	0	0.00
CONT_ASSIGN	81	1	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	100	1	0	0.00
CONT_ASSIGN	101	1	0	0.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	138	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	0	1
70	0	1
71	0	1
72	0	1
			==> MISSING_ELSE
81	0	1
82	0	1
100	0	1
101	0	1
108	0	1
111	0	1
112	0	1
			==> MISSING_ELSE
116	0	1
133	0	1
134	0	1
138	0	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	0	0.00
Logical	16	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	0	0.00
TERNARY	138	2	0	0.00
IF	69	3	0	0.00
IF	123	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	0	0.00
ALWAYS	69	4	0	0.00
CONT_ASSIGN	81	1	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	100	1	0	0.00
CONT_ASSIGN	101	1	0	0.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	0	0.00
CONT_ASSIGN	138	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	0	1
70	0	1
71	0	1
72	0	1
			==> MISSING_ELSE
81	0	1
82	0	1
100	0	1
101	0	1
108	0	1
111	0	1
112	0	1
			==> MISSING_ELSE
116	0	1
133	0	1
134	0	1
138	0	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	0	0.00
Logical	16	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	0	0.00
TERNARY	138	2	0	0.00
IF	69	3	0	0.00
IF	123	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	0	0.00
ALWAYS	69	4	0	0.00
CONT_ASSIGN	81	1	0	0.00
CONT_ASSIGN	82	1	0	0.00
CONT_ASSIGN	100	1	0	0.00
CONT_ASSIGN	101	1	0	0.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	130	1	0	0.00
CONT_ASSIGN	131	1	0	0.00
CONT_ASSIGN	138	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	0	1
70	0	1
71	0	1
72	0	1
			==> MISSING_ELSE
81	0	1
82	0	1
100	0	1
101	0	1
108	0	1
111	0	1
112	0	1
			==> MISSING_ELSE
116	0	1
130	0	1
131	0	1
138	0	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	0	0.00
Logical	24	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	0	0.00
TERNARY	130	2	0	0.00
TERNARY	138	2	0	0.00
IF	69	3	0	0.00
IF	111	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered