Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.03	97.53	88.06	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	365426275	12099	0	0
ep_in_enable_rd_A	365426275	3109	0	0
ep_out_enable_rd_A	365426275	3315	0	0
in_iso_rd_A	365426275	3042	0	0
intr_enable_rd_A	365426275	4408	0	0
out_iso_rd_A	365426275	3186	0	0
phy_config_rd_A	365426275	1988	0	0
phy_pins_drive_rd_A	365426275	2785	0	0
rxenable_setup_rd_A	365426275	2895	0	0
set_nak_out_rd_A	365426275	3112	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365426275	12099	0	0
T198	4910	5	0	0
T199	6506	970	0	0
T200	6526	9	0	0
T222	4757	25	0	0
T223	21872	2	0	0
T224	106153	6	0	0
T225	9502	26	0	0
T230	26953	2	0	0
T231	5579	8	0	0
T280	34803	3	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365426275	3109	0	0
T198	4910	41	0	0
T223	21872	245	0	0
T226	3679	4	0	0
T231	5579	26	0	0
T232	9267	115	0	0
T244	6589	33	0	0
T261	2972	1	0	0
T263	77915	390	0	0
T275	3224	1	0	0
T276	4774	48	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365426275	3315	0	0
T198	4910	8	0	0
T223	21872	286	0	0
T226	3679	4	0	0
T231	5579	49	0	0
T232	9267	59	0	0
T244	6589	41	0	0
T261	2972	26	0	0
T263	77915	435	0	0
T275	3224	18	0	0
T276	4774	24	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365426275	3042	0	0
T198	4910	7	0	0
T223	21872	217	0	0
T226	3679	5	0	0
T231	5579	54	0	0
T232	9267	95	0	0
T244	6589	12	0	0
T261	2972	48	0	0
T263	77915	441	0	0
T275	3224	30	0	0
T276	4774	22	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365426275	4408	0	0
T198	4910	42	0	0
T207	2400	1	0	0
T209	2373	13	0	0
T223	21872	323	0	0
T226	3679	156	0	0
T231	5579	72	0	0
T232	9267	102	0	0
T244	6589	66	0	0
T261	2972	6	0	0
T276	4774	6	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365426275	3186	0	0
T198	4910	39	0	0
T223	21872	197	0	0
T226	3679	80	0	0
T231	5579	57	0	0
T232	9267	91	0	0
T244	6589	53	0	0
T261	2972	45	0	0
T263	77915	470	0	0
T276	4774	23	0	0
T281	3765	59	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365426275	1988	0	0
T198	4910	18	0	0
T223	21872	127	0	0
T226	3679	30	0	0
T231	5579	9	0	0
T232	9267	9	0	0
T244	6589	20	0	0
T261	2972	15	0	0
T263	77915	381	0	0
T275	3224	2	0	0
T281	3765	3	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365426275	2785	0	0
T198	4910	1	0	0
T223	21872	187	0	0
T226	3679	31	0	0
T231	5579	3	0	0
T232	9267	67	0	0
T244	6589	8	0	0
T261	2972	2	0	0
T263	77915	456	0	0
T275	3224	9	0	0
T276	4774	6	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365426275	2895	0	0
T198	4910	28	0	0
T223	21872	311	0	0
T226	3679	52	0	0
T231	5579	9	0	0
T232	9267	56	0	0
T244	6589	7	0	0
T261	2972	1	0	0
T263	77915	441	0	0
T275	3224	38	0	0
T276	4774	39	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	365426275	3112	0	0
T223	21872	244	0	0
T226	3679	80	0	0
T231	5579	27	0	0
T232	9267	54	0	0
T244	6589	6	0	0
T261	2972	33	0	0
T263	77915	458	0	0
T275	3224	31	0	0
T276	4774	6	0	0
T281	3765	6	0	0