Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : usbdev
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.03 97.53 88.06 94.55 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 96.03 97.53 88.06 94.55 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.03 97.53 88.06 94.55 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.08 97.84 93.79 97.44 75.00 96.26 98.17


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_event 100.00 100.00 100.00
gen_no_stubbed_memory.u_memory_1p 99.02 97.06 100.00 100.00
gen_no_stubbed_memory.u_tlul2sram 85.96 86.89 75.84 81.11 100.00
i_usbdev_iomux 81.94 100.00 77.78 100.00 50.00
intr_av_out_empty 86.94 90.00 77.78 80.00 100.00
intr_av_overflow 91.67 100.00 66.67 100.00 100.00
intr_av_setup_empty 86.94 90.00 77.78 80.00 100.00
intr_disconnected 93.75 100.00 75.00 100.00 100.00
intr_frame 89.58 100.00 58.33 100.00 100.00
intr_host_lost 93.75 100.00 75.00 100.00 100.00
intr_hw_pkt_received 86.94 90.00 77.78 80.00 100.00
intr_hw_pkt_sent 86.94 90.00 77.78 80.00 100.00
intr_link_in_err 89.58 100.00 58.33 100.00 100.00
intr_link_out_err 93.75 100.00 75.00 100.00 100.00
intr_link_reset 93.75 100.00 75.00 100.00 100.00
intr_link_resume 89.58 100.00 58.33 100.00 100.00
intr_link_suspend 89.58 100.00 58.33 100.00 100.00
intr_powered 89.58 100.00 58.33 100.00 100.00
intr_rx_bitstuff_err 89.58 100.00 58.33 100.00 100.00
intr_rx_crc_err 93.75 100.00 75.00 100.00 100.00
intr_rx_full 86.94 90.00 77.78 80.00 100.00
intr_rx_pid_err 93.75 100.00 75.00 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_ctr_errors 57.70 84.21 33.33 55.56
u_ctr_in 51.16 78.95 20.00 54.55
u_ctr_nodata_in 59.59 84.21 40.00 54.55
u_ctr_out 51.16 78.95 20.00 54.55
u_reg 97.78 98.85 98.09 100.00 98.41 93.55
usbdev_avoutfifo 97.06 100.00 88.24 100.00 100.00
usbdev_avsetupfifo 97.06 100.00 88.24 100.00 100.00
usbdev_csr_assert 100.00 100.00
usbdev_impl 92.46 98.07 95.10 75.00 94.12 100.00
usbdev_rxfifo 96.53 100.00 86.11 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : usbdev
Line No.TotalCoveredPercent
TOTAL16215897.53
CONT_ASSIGN12311100.00
CONT_ASSIGN16711100.00
CONT_ASSIGN22011100.00
ALWAYS22255100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN25811100.00
CONT_ASSIGN25911100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26411100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26811100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN32111100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32711100.00
CONT_ASSIGN35211100.00
CONT_ASSIGN35311100.00
CONT_ASSIGN35411100.00
CONT_ASSIGN35511100.00
CONT_ASSIGN35611100.00
CONT_ASSIGN360100.00
ALWAYS38300
ALWAYS38333100.00
ALWAYS39100
ALWAYS39144100.00
ALWAYS40000
ALWAYS40033100.00
ALWAYS40700
ALWAYS40733100.00
ALWAYS41400
ALWAYS41433100.00
ALWAYS42100
ALWAYS42122100.00
ALWAYS43455100.00
CONT_ASSIGN44211100.00
CONT_ASSIGN44311100.00
CONT_ASSIGN44711100.00
CONT_ASSIGN44811100.00
CONT_ASSIGN44911100.00
CONT_ASSIGN45111100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45711100.00
CONT_ASSIGN45811100.00
CONT_ASSIGN46011100.00
ALWAYS46433100.00
ALWAYS47100
ALWAYS47133100.00
ALWAYS48033100.00
ALWAYS49233100.00
ALWAYS49900
ALWAYS49933100.00
ALWAYS5061010100.00
ALWAYS52533100.00
ALWAYS53200
ALWAYS53233100.00
ALWAYS54000
ALWAYS54033100.00
ALWAYS54900
ALWAYS54933100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56011100.00
CONT_ASSIGN56111100.00
CONT_ASSIGN68411100.00
CONT_ASSIGN68511100.00
CONT_ASSIGN68711100.00
CONT_ASSIGN68811100.00
CONT_ASSIGN70611100.00
CONT_ASSIGN70911100.00
ALWAYS71500
ALWAYS71588100.00
CONT_ASSIGN80011100.00
CONT_ASSIGN80111100.00
CONT_ASSIGN80211100.00
CONT_ASSIGN80311100.00
CONT_ASSIGN81111100.00
ALWAYS82088100.00
CONT_ASSIGN83411100.00
CONT_ASSIGN83500
CONT_ASSIGN83811100.00
CONT_ASSIGN83911100.00
CONT_ASSIGN89711100.00
CONT_ASSIGN89811100.00
CONT_ASSIGN90211100.00
CONT_ASSIGN116511100.00
CONT_ASSIGN116611100.00
CONT_ASSIGN116711100.00
CONT_ASSIGN116811100.00
CONT_ASSIGN120811100.00
CONT_ASSIGN121111100.00
CONT_ASSIGN122011100.00
ALWAYS122355100.00
ALWAYS123233100.00
CONT_ASSIGN124511100.00
CONT_ASSIGN124811100.00
CONT_ASSIGN125511100.00
ALWAYS125933100.00
CONT_ASSIGN126611100.00
CONT_ASSIGN127111100.00
CONT_ASSIGN127311100.00
CONT_ASSIGN128111100.00
CONT_ASSIGN128311100.00
CONT_ASSIGN128511100.00
CONT_ASSIGN128711100.00
CONT_ASSIGN1297100.00
CONT_ASSIGN1301100.00
CONT_ASSIGN1304100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
123 1 1
167 1 1
220 1 1
222 1 1
223 1 1
225 1 1
226 1 1
228 1 1
257 1 1
258 1 1
259 1 1
263 1 1
264 1 1
266 1 1
268 1 1
316 1 1
321 1 1
324 1 1
327 1 1
352 1 1
353 1 1
354 1 1
355 1 1
356 1 1
360 0 1
383 1 1
384 1 1
385 1 1
391 1 1
392 1 1
393 1 1
394 1 1
400 1 1
401 1 1
402 1 1
407 1 1
408 1 1
409 1 1
414 1 1
415 1 1
416 1 1
421 1 1
422 1 1
434 1 1
435 1 1
436 1 1
438 1 1
439 1 1
442 1 1
443 1 1
447 1 1
448 1 1
449 1 1
451 1 1
456 1 1
457 1 1
458 1 1
460 1 1
464 1 1
465 1 1
466 1 1
MISSING_ELSE
471 1 1
472 1 1
473 1 1
480 1 1
481 1 1
482 1 1
492 1 1
493 1 1
494 1 1
MISSING_ELSE
499 1 1
500 1 1
501 1 1
506 1 1
507 1 1
508 1 1
509 1 1
510 1 1
512 1 1
514 1 1
515 1 1
516 1 1
518 1 1
MISSING_ELSE
525 1 1
526 2 2
MISSING_ELSE
532 1 1
533 1 1
534 1 1
540 1 1
541 1 1
542 1 1
549 1 1
550 1 1
551 1 1
559 1 1
560 1 1
561 1 1
684 1 1
685 1 1
687 1 1
688 1 1
706 1 1
709 1 1
715 1 1
716 1 1
717 1 1
718 1 1
719 1 1
720 1 1
722 1 1
723 1 1
800 1 1
801 1 1
802 1 1
803 1 1
811 1 1
820 1 1
821 1 1
822 1 1
823 1 1
825 1 1
826 1 1
828 1 1
829 1 1
MISSING_ELSE
834 1 1
835 unreachable
838 1 1
839 1 1
897 1 1
898 1 1
902 1 1
1165 1 1
1166 1 1
1167 1 1
1168 1 1
1208 1 1
1211 1 1
1220 1 1
1223 1 1
1224 1 1
1225 1 1
1226 1 1
1227 1 1
MISSING_ELSE
1232 1 1
1233 1 1
1235 1 1
1245 1 1
1248 1 1
1255 1 1
1259 1 1
1260 1 1
1262 1 1
1266 1 1
1271 1 1
1273 1 1
1281 1 1
1283 1 1
1285 1 1
1287 1 1
1297 0 1
1301 0 1
1304 0 1


Cond Coverage for Module : usbdev
TotalCoveredPercent
Conditions13411888.06
Logical13411888.06
Non-Logical00
Event00

 LINE       167
 EXPRESSION (event_rx_crc5_err | event_rx_crc16_err)
             --------1--------   ---------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT62,T50,T73
10CoveredT73,T46,T74

 LINE       220
 EXPRESSION (ns_cnt == 6'd47)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       257
 EXPRESSION (reg2hw.fifo_ctrl.avsetup_rst.qe & reg2hw.fifo_ctrl.avsetup_rst.q)
             ---------------1---------------   ---------------2--------------
-1--2-StatusTests
01CoveredT81,T43,T90
10CoveredT81,T188,T189
11CoveredT81,T43,T90

 LINE       258
 EXPRESSION (reg2hw.fifo_ctrl.avout_rst.qe & reg2hw.fifo_ctrl.avout_rst.q)
             --------------1--------------   --------------2-------------
-1--2-StatusTests
01CoveredT81,T43,T90
10CoveredT81,T188,T189
11CoveredT81,T43,T90

 LINE       259
 EXPRESSION (reg2hw.fifo_ctrl.rx_rst.qe & reg2hw.fifo_ctrl.rx_rst.q)
             -------------1------------   ------------2------------
-1--2-StatusTests
01CoveredT43,T90,T96
10CoveredT81,T188,T189
11CoveredT43,T90,T96

 LINE       263
 EXPRESSION (connect_en & ((~avsetup_rvalid)))
             -----1----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T33
11CoveredT1,T2,T3

 LINE       264
 EXPRESSION (connect_en & ((~avout_rvalid)))
             -----1----   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       266
 EXPRESSION ((reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready))) | (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready))))
             --------------------------1-------------------------   ------------------------2-----------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT67,T86
10CoveredT65,T66,T85

 LINE       266
 SUB-EXPRESSION (reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready)))
                 -----------1-----------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T4,T33
11CoveredT65,T66,T85

 LINE       266
 SUB-EXPRESSION (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready)))
                 ----------1----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT67,T86

 LINE       268
 EXPRESSION (connect_en & ((~rx_fifo_rvalid)))
             -----1----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       316
 EXPRESSION (reg2hw.rxfifo.ep.re | reg2hw.rxfifo.setup.re | reg2hw.rxfifo.size.re | reg2hw.rxfifo.buffer.re)
             ---------1---------   -----------2----------   ----------3----------   -----------4-----------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Not Covered
0010Not Covered
0100Not Covered
1000Not Covered

 LINE       327
 EXPRESSION (rx_wready & (rx_depth < 4'((RXFifoDepth - 1))))
             ----1----   -----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT43,T54,T94
11CoveredT1,T2,T3

 LINE       442
 EXPRESSION (in_xact_starting ? in_buf[in_xact_start_ep] : in_buf_q)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T28

 LINE       443
 EXPRESSION (in_xact_starting ? in_size[in_xact_start_ep] : in_size_q)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T28

 LINE       447
 EXPRESSION (reg2hw.out_data_toggle.status.qe & reg2hw.out_data_toggle.mask.qe)
             ----------------1---------------   ---------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T61,T103

 LINE       456
 EXPRESSION (reg2hw.in_data_toggle.status.qe & reg2hw.in_data_toggle.mask.qe)
             ---------------1---------------   --------------2--------------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T61,T103

 LINE       465
 EXPRESSION (in_ep_xact_end && in_endpoint_val)
             -------1------    -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT1,T2,T28

 LINE       493
 EXPRESSION (rx_wvalid && out_endpoint_val)
             ----1----    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT1,T2,T3

 LINE       512
 EXPRESSION (setup_received & out_endpoint_val)
             -------1------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT4,T33,T51

 LINE       516
 EXPRESSION (in_ep_xact_end & in_endpoint_val)
             -------1------   -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Unreachable
11CoveredT1,T2,T28

 LINE       542
 EXPRESSION (reg2hw.configin[i].rdy.q | reg2hw.configin[i].pend.q)
             ------------1-----------   ------------2------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT43,T170,T152
10CoveredT1,T2,T28

 LINE       550
 EXPRESSION (set_sending[i] | set_sentbit[i] | update_pend[i])
             -------1------   -------2------   -------3------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T2,T3
010CoveredT1,T2,T28
100CoveredT1,T2,T28

 LINE       551
 EXPRESSION (((~set_sentbit[i])) & ((~update_pend[i])))
             ---------1---------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T28
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       560
 EXPRESSION (cfg_pinflip ? 1'b0 : usb_pullup_en)
             -----1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T9,T80

 LINE       561
 EXPRESSION (((!cfg_pinflip)) ? 1'b0 : usb_pullup_en)
             --------1-------
-1-StatusTests
0CoveredT8,T9,T80
1CoveredT1,T2,T3

 LINE       688
 EXPRESSION (reg2hw.usbctrl.resume_link_active.qe & reg2hw.usbctrl.resume_link_active.q)
             ------------------1-----------------   -----------------2-----------------
-1--2-StatusTests
01CoveredT49
10CoveredT1,T2,T3
11CoveredT49

 LINE       800
 EXPRESSION (usb_mem_b_req | sw_mem_a_req)
             ------1------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T29
10CoveredT1,T2,T3

 LINE       801
 EXPRESSION (usb_mem_b_req ? usb_mem_b_write : sw_mem_a_write)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       802
 EXPRESSION (usb_mem_b_req ? usb_mem_b_addr : sw_mem_a_addr)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       803
 EXPRESSION (usb_mem_b_req ? usb_mem_b_wdata : sw_mem_a_wdata)
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       826
 EXPRESSION (usb_mem_b_req & ((!usb_mem_b_write)))
             ------1------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T28

 LINE       834
 EXPRESSION (gen_no_stubbed_memory.mem_rvalid & ((!gen_no_stubbed_memory.mem_rsteering)))
             ----------------1---------------   --------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T28
11CoveredT1,T3,T29

 LINE       839
 EXPRESSION (gen_no_stubbed_memory.mem_b_read_q ? gen_no_stubbed_memory.mem_rdata : gen_no_stubbed_memory.mem_b_rdata_q)
             -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T28

 LINE       902
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01CoveredT21,T190,T191
10CoveredT1,T2,T3
11CoveredT21,T190,T191

 LINE       1211
 EXPRESSION (use_diff_rcvr & ((~link_suspend)))
             ------1------   --------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT28,T6,T7
11CoveredT1,T2,T3

 LINE       1220
 EXPRESSION (usb_rcvr_ok_counter_q == '0)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1224
 EXPRESSION (use_diff_rcvr & ((!usb_rx_enable_o)))
             ------1------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT28,T6,T7

 LINE       1226
 EXPRESSION (us_tick && (usb_rcvr_ok_counter_q > '0))
             ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT192,T193,T151

 LINE       1248
 EXPRESSION (usb_ref_disable ? 1'b0 : event_sof)
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38,T39,T194

 LINE       1255
 EXPRESSION (usb_ref_pulse_o ? 1'b1 : ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q))
             -------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38,T39,T40

 LINE       1255
 SUB-EXPRESSION ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q)
                 -------------------------1------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1255
 SUB-EXPRESSION (((!link_active)) || host_lost || usb_ref_disable)
                 --------1-------    ----2----    -------3-------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT38,T39,T194
010CoveredT2,T4,T5
100CoveredT1,T2,T3

 LINE       1271
 EXPRESSION (reg2hw.wake_control.suspend_req.qe & reg2hw.wake_control.suspend_req.q)
             -----------------1----------------   ----------------2----------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT6,T7,T8
11CoveredT6,T7,T8

 LINE       1273
 EXPRESSION (reg2hw.wake_control.wake_ack.qe & reg2hw.wake_control.wake_ack.q)
             ---------------1---------------   ---------------2--------------
-1--2-StatusTests
01CoveredT6,T7,T8
10CoveredT6,T7,T8
11CoveredT6,T7,T8

 LINE       1310
 EXPRESSION (reg2hw.count_out.rst.qe & reg2hw.count_out.rst.q)
             -----------1-----------   -----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       1336
 EXPRESSION (reg2hw.count_in.rst.qe & reg2hw.count_in.rst.q)
             -----------1----------   ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       1359
 EXPRESSION (reg2hw.count_nodata_in.rst.qe & reg2hw.count_nodata_in.rst.q)
             --------------1--------------   --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       1376
 EXPRESSION (reg2hw.count_errors.rst.qe & reg2hw.count_errors.rst.q)
             -------------1------------   ------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

Toggle Coverage for Module : usbdev
TotalCoveredPercent
Totals 74 68 91.89
Total Bits 440 416 94.55
Total Bits 0->1 220 208 94.55
Total Bits 1->0 220 208 94.55

Ports 74 68 91.89
Port Bits 440 416 94.55
Port Bits 0->1 220 208 94.55
Port Bits 1->0 220 208 94.55

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T195,T196,T197 Yes T1,T2,T3 INPUT
clk_aon_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_aon_ni Yes Yes T195,T196,T197 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T3,T28,T29 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T29,T4 Yes T1,T29,T4 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T28 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T28 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T3,T29 Yes T1,T3,T28 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T198,T199,T200 Yes T198,T199,T200 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T3,T29 Yes T1,T3,T28 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T21,T190,T191 Yes T21,T190,T191 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T21,T190,T191 Yes T21,T190,T191 OUTPUT
cio_usb_dp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
cio_usb_dn_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
usb_rx_d_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
cio_usb_dp_o Yes Yes T1,T2,T28 Yes T1,T2,T28 OUTPUT
cio_usb_dp_en_o Yes Yes T1,T2,T28 Yes T1,T2,T28 OUTPUT
cio_usb_dn_o Yes Yes T1,T2,T28 Yes T1,T2,T28 OUTPUT
cio_usb_dn_en_o Yes Yes T1,T2,T28 Yes T1,T2,T28 OUTPUT
usb_tx_se0_o Yes Yes T1,T2,T28 Yes T1,T2,T28 OUTPUT
usb_tx_d_o Yes Yes T1,T2,T28 Yes T1,T2,T28 OUTPUT
cio_sense_i Yes Yes T9,T10,T14 Yes T1,T2,T3 INPUT
usb_dp_pullup_o Yes Yes T6,T7,T8 Yes T1,T2,T3 OUTPUT
usb_dn_pullup_o Yes Yes T8,T9,T201 Yes T8,T9,T80 OUTPUT
usb_rx_enable_o Yes Yes T28,T6,T7 Yes T1,T2,T3 OUTPUT
usb_tx_use_d_se0_o Yes Yes T198,T200,T202 Yes T203,T204,T205 OUTPUT
usb_aon_suspend_req_o Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
usb_aon_wake_ack_o Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
usb_aon_bus_reset_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
usb_aon_sense_lost_i Yes Yes T9,T10,T14 Yes T9,T10,T14 INPUT
usb_aon_bus_not_idle_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
usb_aon_wake_detect_active_i Yes Yes T6,T7,T8 Yes T6,T7,T8 INPUT
usb_ref_val_o Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
usb_ref_pulse_o Yes Yes T38,T39,T40 Yes T38,T39,T40 OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
intr_pkt_received_o Yes Yes T31,T33,T51 Yes T31,T33,T51 OUTPUT
intr_pkt_sent_o Yes Yes T28,T29,T6 Yes T28,T29,T6 OUTPUT
intr_powered_o Yes Yes T206,T207,T208 Yes T206,T207,T208 OUTPUT
intr_disconnected_o Yes Yes T40,T47,T48 Yes T40,T47,T48 OUTPUT
intr_host_lost_o Yes Yes T68,T209,T206 Yes T68,T209,T206 OUTPUT
intr_link_reset_o Yes Yes T69,T209,T206 Yes T69,T209,T206 OUTPUT
intr_link_suspend_o Yes Yes T209,T206,T207 Yes T209,T206,T207 OUTPUT
intr_link_resume_o Yes Yes T209,T206,T207 Yes T209,T206,T207 OUTPUT
intr_av_out_empty_o Yes Yes T52,T53,T209 Yes T52,T53,T209 OUTPUT
intr_rx_full_o Yes Yes T54,T209,T206 Yes T54,T209,T206 OUTPUT
intr_av_overflow_o Yes Yes T65,T66,T67 Yes T65,T66,T67 OUTPUT
intr_link_in_err_o Yes Yes T209,T206,T207 Yes T209,T206,T207 OUTPUT
intr_link_out_err_o Yes Yes T70,T71,T72 Yes T70,T71,T72 OUTPUT
intr_rx_crc_err_o Yes Yes T50,T74,T75 Yes T50,T74,T75 OUTPUT
intr_rx_pid_err_o Yes Yes T76,T77,T78 Yes T76,T77,T78 OUTPUT
intr_rx_bitstuff_err_o Yes Yes T206,T207,T208 Yes T206,T207,T208 OUTPUT
intr_frame_o Yes Yes T209,T206,T208 Yes T209,T206,T208 OUTPUT
intr_av_setup_empty_o Yes Yes T58,T59,T60 Yes T58,T59,T60 OUTPUT

*Tests covering at least one bit in the range

Branch Coverage for Module : usbdev
Line No.TotalCoveredPercent
Branches 48 48 100.00
TERNARY 442 2 2 100.00
TERNARY 443 2 2 100.00
TERNARY 560 2 2 100.00
TERNARY 561 2 2 100.00
TERNARY 1248 2 2 100.00
TERNARY 1255 3 3 100.00
TERNARY 801 2 2 100.00
TERNARY 802 2 2 100.00
TERNARY 803 2 2 100.00
TERNARY 839 2 2 100.00
IF 222 3 3 100.00
IF 434 2 2 100.00
IF 465 2 2 100.00
IF 493 2 2 100.00
IF 508 4 4 100.00
IF 526 2 2 100.00
IF 718 2 2 100.00
IF 1224 3 3 100.00
IF 1232 2 2 100.00
IF 1259 2 2 100.00
IF 820 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 442 (in_xact_starting) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 443 (in_xact_starting) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 560 (cfg_pinflip) ?

Branches:
-1-StatusTests
1 Covered T8,T9,T80
0 Covered T1,T2,T3


LineNo. Expression -1-: 561 ((!cfg_pinflip)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T8,T9,T80


LineNo. Expression -1-: 1248 (usb_ref_disable) ?

Branches:
-1-StatusTests
1 Covered T38,T39,T194
0 Covered T1,T2,T3


LineNo. Expression -1-: 1255 (usb_ref_pulse_o) ? -2-: 1255 ((((!link_active) || host_lost) || usb_ref_disable)) ?

Branches:
-1--2-StatusTests
1 - Covered T38,T39,T40
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 801 (usb_mem_b_req) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 802 (usb_mem_b_req) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 803 (usb_mem_b_req) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 839 (gen_no_stubbed_memory.mem_b_read_q) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 222 if ((!rst_n)) -2-: 225 if (us_tick)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 434 if ((!rst_n))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 465 if ((in_ep_xact_end && in_endpoint_val))

Branches:
-1-StatusTests
1 Covered T1,T2,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 493 if ((rx_wvalid && out_endpoint_val))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 508 if (event_link_reset) -2-: 512 if ((setup_received & out_endpoint_val)) -3-: 516 if ((in_ep_xact_end & in_endpoint_val))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T4,T33,T51
0 0 1 Covered T1,T2,T28
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 526 if (in_xact_starting)

Branches:
-1-StatusTests
1 Covered T1,T2,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 718 if (((setup_received && out_endpoint_val) && (out_endpoint == 4'((unsigned'(i))))))

Branches:
-1-StatusTests
1 Covered T4,T33,T51
0 Covered T1,T2,T3


LineNo. Expression -1-: 1224 if ((use_diff_rcvr & (!usb_rx_enable_o))) -2-: 1226 if ((us_tick && (usb_rcvr_ok_counter_q > '0)))

Branches:
-1--2-StatusTests
1 - Covered T28,T6,T7
0 1 Covered T192,T193,T151
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1232 if ((!rst_n))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 1259 if ((!rst_n))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 820 if ((!rst_ni)) -2-: 828 if (gen_no_stubbed_memory.mem_b_read_q)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T28
0 0 Covered T1,T2,T3


Assert Coverage for Module : usbdev
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 35 35 100.00 35 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 35 35 100.00 35 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertsKnown_A 363588127 363390813 0 0
CIODnEnKnown_A 363588127 363390813 0 0
CIODnKnown_A 363588127 363390813 0 0
CIODpEnKnown_A 363588127 363390813 0 0
CIODpKnown_A 363588127 363390813 0 0
FpvSecCmRegWeOnehotCheck_A 363588127 80 0 0
TlOAReadyKnown_A 363588127 363390813 0 0
TlODValidKnown_A 363588127 363390813 0 0
USBAonSuspendReqKnown_A 363588127 363390813 0 0
USBAonWakeAckKnown_A 363588127 363390813 0 0
USBDnPUKnown_A 363588127 363390813 0 0
USBDpPUKnown_A 363588127 363390813 0 0
USBIntrAvOutEmptyKnown_A 363588127 363390813 0 0
USBIntrAvOverKnown_A 363588127 363390813 0 0
USBIntrAvSetupEmptyKnown_A 363588127 363390813 0 0
USBIntrDisConKnown_A 363588127 363390813 0 0
USBIntrFrameKnown_A 363588127 363390813 0 0
USBIntrHostLostKnown_A 363588127 363390813 0 0
USBIntrLinkInErrKnown_A 363588127 363390813 0 0
USBIntrLinkOutErrKnown_A 363588127 363390813 0 0
USBIntrLinkResKnown_A 363588127 363390813 0 0
USBIntrLinkRstKnown_A 363588127 363390813 0 0
USBIntrLinkSusKnown_A 363588127 363390813 0 0
USBIntrPktRcvdKnown_A 363588127 363390813 0 0
USBIntrPktSentKnown_A 363588127 363390813 0 0
USBIntrPwrdKnown_A 363588127 363390813 0 0
USBIntrRxBitstuffErrKnown_A 363588127 363390813 0 0
USBIntrRxCrCErrKnown_A 363588127 363390813 0 0
USBIntrRxFullKnown_A 363588127 363390813 0 0
USBIntrRxPidErrKnown_A 363588127 363390813 0 0
USBRefPulseKnown_A 363588127 363390813 0 0
USBRefValKnown_A 363588127 363390813 0 0
USBRxEnableKnown_A 363588127 363390813 0 0
USBTxDKnown_A 363588127 363390813 0 0
USBTxSe0Known_A 363588127 363390813 0 0


AlertsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

CIODnEnKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

CIODnKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

CIODpEnKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

CIODpKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 80 0 0
T66 6550 0 0 0
T195 46776 10 0 0
T196 0 20 0 0
T197 0 20 0 0
T210 0 20 0 0
T211 0 10 0 0
T212 9509 0 0 0
T213 10276 0 0 0
T214 10374 0 0 0
T215 6765 0 0 0
T216 11787 0 0 0
T217 439750 0 0 0
T218 16697 0 0 0
T219 7227 0 0 0

TlOAReadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

TlODValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBAonSuspendReqKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBAonWakeAckKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBDnPUKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBDpPUKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrAvOutEmptyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrAvOverKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrAvSetupEmptyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrDisConKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrFrameKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrHostLostKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrLinkInErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrLinkOutErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrLinkResKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrLinkRstKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrLinkSusKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrPktRcvdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrPktSentKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrPwrdKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrRxBitstuffErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrRxCrCErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrRxFullKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBIntrRxPidErrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBRefPulseKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBRefValKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBRxEnableKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBTxDKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

USBTxSe0Known_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 363588127 363390813 0 0
T1 21306 21241 0 0
T2 211591 211513 0 0
T3 9078 8991 0 0
T4 201620 201528 0 0
T28 158814 158748 0 0
T29 39134 39069 0 0
T30 12442 12348 0 0
T31 8074 7991 0 0
T32 9155 9104 0 0
T33 9395 9305 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%