Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	392	1		T1	2		T3	2		T7	2
all_values[1]	392	1		T1	2		T3	2		T7	2
all_values[2]	392	1		T1	2		T3	2		T7	2
all_values[3]	392	1		T1	2		T3	2		T7	2
all_values[4]	392	1		T1	2		T3	2		T7	2
all_values[5]	392	1		T1	2		T3	2		T7	2
all_values[6]	392	1		T1	2		T3	2		T7	2
all_values[7]	392	1		T1	2		T3	2		T7	2
all_values[8]	392	1		T1	2		T3	2		T7	2
all_values[9]	392	1		T1	2		T3	2		T7	2
all_values[10]	392	1		T1	2		T3	2		T7	2
all_values[11]	392	1		T1	2		T3	2		T7	2
all_values[12]	392	1		T1	2		T3	2		T7	2
all_values[13]	392	1		T1	2		T3	2		T7	2
all_values[14]	392	1		T1	2		T3	2		T7	2
all_values[15]	392	1		T1	2		T3	2		T7	2
all_values[16]	392	1		T1	2		T3	2		T7	2
all_values[17]	392	1		T1	2		T3	2		T7	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3932	1		T1	36		T3	36		T7	36
auto[1]	3124	1		T13	70		T14	65		T15	34

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1605	1		T1	36		T3	36		T7	36
auto[1]	5451	1		T13	115		T14	132		T15	82

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	59	1		T1	2		T3	2		T7	2
all_values[0]	auto[0]	auto[1]	141	1		T13	2		T14	1		T15	4
all_values[0]	auto[1]	auto[0]	28	1		T37	2		T18	1		T63	1
all_values[0]	auto[1]	auto[1]	164	1		T13	6		T14	7		T15	1
all_values[1]	auto[0]	auto[0]	73	1		T1	2		T3	2		T7	2
all_values[1]	auto[0]	auto[1]	166	1		T13	4		T14	6		T15	4
all_values[1]	auto[1]	auto[0]	18	1		T16	1		T64	1		T65	2
all_values[1]	auto[1]	auto[1]	135	1		T13	2		T14	2		T15	1
all_values[2]	auto[0]	auto[0]	55	1		T1	2		T3	2		T7	2
all_values[2]	auto[0]	auto[1]	172	1		T13	6		T14	4		T16	5
all_values[2]	auto[1]	auto[0]	17	1		T16	1		T17	1		T66	2
all_values[2]	auto[1]	auto[1]	148	1		T13	2		T14	4		T15	5
all_values[3]	auto[0]	auto[0]	70	1		T1	2		T3	2		T7	2
all_values[3]	auto[0]	auto[1]	144	1		T13	5		T14	6		T16	7
all_values[3]	auto[1]	auto[0]	17	1		T15	1		T19	1		T63	1
all_values[3]	auto[1]	auto[1]	161	1		T13	3		T14	2		T16	1
all_values[4]	auto[0]	auto[0]	71	1		T1	2		T3	2		T7	2
all_values[4]	auto[0]	auto[1]	167	1		T13	6		T14	5		T15	4
all_values[4]	auto[1]	auto[0]	31	1		T19	1		T18	2		T63	2
all_values[4]	auto[1]	auto[1]	123	1		T13	2		T14	1		T15	1
all_values[5]	auto[0]	auto[0]	64	1		T1	2		T3	2		T7	2
all_values[5]	auto[0]	auto[1]	154	1		T13	5		T14	2		T15	4
all_values[5]	auto[1]	auto[0]	32	1		T16	1		T67	3		T68	1
all_values[5]	auto[1]	auto[1]	142	1		T13	2		T14	5		T15	1
all_values[6]	auto[0]	auto[0]	62	1		T1	2		T3	2		T7	2
all_values[6]	auto[0]	auto[1]	149	1		T13	1		T14	2		T15	4
all_values[6]	auto[1]	auto[0]	32	1		T13	1		T14	2		T15	1
all_values[6]	auto[1]	auto[1]	149	1		T13	6		T14	3		T16	4
all_values[7]	auto[0]	auto[0]	67	1		T1	2		T3	2		T7	2
all_values[7]	auto[0]	auto[1]	162	1		T13	4		T14	4		T15	4
all_values[7]	auto[1]	auto[0]	19	1		T17	1		T68	5		T69	1
all_values[7]	auto[1]	auto[1]	144	1		T13	4		T14	4		T15	1
all_values[8]	auto[0]	auto[0]	66	1		T1	2		T3	2		T7	2
all_values[8]	auto[0]	auto[1]	160	1		T13	5		T14	7		T15	3
all_values[8]	auto[1]	auto[0]	27	1		T19	1		T17	2		T66	1
all_values[8]	auto[1]	auto[1]	139	1		T13	3		T14	1		T15	2
all_values[9]	auto[0]	auto[0]	67	1		T1	2		T3	2		T7	2
all_values[9]	auto[0]	auto[1]	142	1		T13	4		T14	1		T16	5
all_values[9]	auto[1]	auto[0]	30	1		T16	1		T19	2		T70	5
all_values[9]	auto[1]	auto[1]	153	1		T13	3		T14	7		T15	5
all_values[10]	auto[0]	auto[0]	62	1		T1	2		T3	2		T7	2
all_values[10]	auto[0]	auto[1]	165	1		T13	3		T14	4		T15	3
all_values[10]	auto[1]	auto[0]	26	1		T13	2		T14	1		T16	2
all_values[10]	auto[1]	auto[1]	139	1		T13	3		T14	1		T15	1
all_values[11]	auto[0]	auto[0]	75	1		T1	2		T3	2		T7	2
all_values[11]	auto[0]	auto[1]	132	1		T14	6		T15	4		T16	3
all_values[11]	auto[1]	auto[0]	21	1		T13	2		T14	1		T16	1
all_values[11]	auto[1]	auto[1]	164	1		T13	5		T14	1		T15	1
all_values[12]	auto[0]	auto[0]	64	1		T1	2		T3	2		T7	2
all_values[12]	auto[0]	auto[1]	145	1		T13	4		T14	3		T15	4
all_values[12]	auto[1]	auto[0]	23	1		T13	1		T37	2		T70	1
all_values[12]	auto[1]	auto[1]	160	1		T13	3		T14	5		T15	1
all_values[13]	auto[0]	auto[0]	61	1		T1	2		T3	2		T7	2
all_values[13]	auto[0]	auto[1]	162	1		T14	4		T15	5		T16	5
all_values[13]	auto[1]	auto[0]	32	1		T13	7		T16	1		T19	1
all_values[13]	auto[1]	auto[1]	137	1		T14	3		T16	2		T19	1
all_values[14]	auto[0]	auto[0]	59	1		T1	2		T3	2		T7	2
all_values[14]	auto[0]	auto[1]	178	1		T13	3		T14	4		T15	5
all_values[14]	auto[1]	auto[0]	30	1		T16	2		T70	1		T63	1
all_values[14]	auto[1]	auto[1]	125	1		T13	1		T14	4		T16	1
all_values[15]	auto[0]	auto[0]	63	1		T1	2		T3	2		T7	2
all_values[15]	auto[0]	auto[1]	150	1		T13	5		T14	6		T15	3
all_values[15]	auto[1]	auto[0]	23	1		T13	1		T17	1		T18	1
all_values[15]	auto[1]	auto[1]	156	1		T14	2		T15	2		T16	3
all_values[16]	auto[0]	auto[0]	55	1		T1	2		T3	2		T7	2
all_values[16]	auto[0]	auto[1]	140	1		T13	3		T14	1		T16	2
all_values[16]	auto[1]	auto[0]	12	1		T15	1		T37	1		T70	1
all_values[16]	auto[1]	auto[1]	185	1		T13	5		T14	7		T15	4
all_values[17]	auto[0]	auto[0]	74	1		T1	2		T3	2		T7	2
all_values[17]	auto[0]	auto[1]	136	1		T13	1		T14	6		T16	4
all_values[17]	auto[1]	auto[0]	20	1		T13	2		T14	1		T19	2
all_values[17]	auto[1]	auto[1]	162	1		T13	4		T14	1		T15	5