| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 68.32 | 66.34 | 60.04 | 86.78 | 0.00 | 70.29 | 98.60 | 96.22 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP | |||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 53.01 | 53.01 | 61.91 | 61.91 | 49.92 | 49.92 | 84.15 | 84.15 | 0.00 | 0.00 | 63.00 | 63.00 | 93.85 | 93.85 | 18.20 | 18.20 | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4259292063 |
| 60.50 | 7.49 | 62.84 | 0.93 | 51.15 | 1.23 | 88.26 | 4.11 | 0.00 | 0.00 | 63.25 | 0.24 | 93.85 | 0.00 | 64.14 | 45.95 | /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2082487209 |
| 63.84 | 3.34 | 63.99 | 1.15 | 53.90 | 2.75 | 90.02 | 1.76 | 0.00 | 0.00 | 63.33 | 0.08 | 95.81 | 1.96 | 79.82 | 15.68 | /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2230011292 |
| 66.44 | 2.61 | 66.15 | 2.16 | 59.76 | 5.86 | 92.61 | 2.58 | 0.00 | 0.00 | 70.13 | 6.80 | 96.65 | 0.84 | 79.82 | 0.00 | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2690364059 |
| 67.50 | 1.05 | 66.15 | 0.00 | 59.76 | 0.00 | 93.31 | 0.70 | 0.00 | 0.00 | 70.13 | 0.00 | 96.65 | 0.00 | 86.49 | 6.67 | /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3111751106 |
| 68.45 | 0.95 | 66.19 | 0.04 | 59.88 | 0.12 | 95.07 | 1.76 | 0.00 | 0.00 | 70.21 | 0.08 | 96.65 | 0.00 | 91.17 | 4.68 | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.505092259 |
| 68.78 | 0.33 | 66.34 | 0.15 | 59.88 | 0.00 | 95.54 | 0.47 | 0.00 | 0.00 | 70.21 | 0.00 | 98.32 | 1.68 | 91.17 | 0.00 | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3775132075 |
| 69.09 | 0.31 | 66.34 | 0.00 | 59.88 | 0.00 | 95.54 | 0.00 | 0.00 | 0.00 | 70.21 | 0.00 | 98.32 | 0.00 | 93.33 | 2.16 | /workspace/coverage/cover_reg_top/43.usbdev_intr_test.4227479040 |
| 69.27 | 0.18 | 66.34 | 0.00 | 59.88 | 0.00 | 95.54 | 0.00 | 0.00 | 0.00 | 70.21 | 0.00 | 98.32 | 0.00 | 94.59 | 1.26 | /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2996887726 |
| 69.35 | 0.08 | 66.34 | 0.00 | 59.88 | 0.00 | 95.54 | 0.00 | 0.00 | 0.00 | 70.21 | 0.00 | 98.32 | 0.00 | 95.14 | 0.54 | /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2035477793 |
| 69.42 | 0.08 | 66.34 | 0.00 | 59.88 | 0.00 | 95.54 | 0.00 | 0.00 | 0.00 | 70.21 | 0.00 | 98.32 | 0.00 | 95.68 | 0.54 | /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3830087472 |
| 69.48 | 0.05 | 66.34 | 0.00 | 59.88 | 0.00 | 95.54 | 0.00 | 0.00 | 0.00 | 70.21 | 0.00 | 98.32 | 0.00 | 96.04 | 0.36 | /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2688518944 |
| 69.51 | 0.04 | 66.34 | 0.00 | 59.88 | 0.00 | 95.54 | 0.00 | 0.00 | 0.00 | 70.21 | 0.00 | 98.60 | 0.28 | 96.04 | 0.00 | /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3873142711 |
| 69.54 | 0.03 | 66.34 | 0.00 | 59.88 | 0.00 | 95.54 | 0.00 | 0.00 | 0.00 | 70.21 | 0.00 | 98.60 | 0.00 | 96.22 | 0.18 | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.311095458 |
| 69.56 | 0.02 | 66.34 | 0.00 | 59.93 | 0.05 | 95.54 | 0.00 | 0.00 | 0.00 | 70.29 | 0.08 | 98.60 | 0.00 | 96.22 | 0.00 | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2315754037 |
| 69.57 | 0.01 | 66.34 | 0.00 | 60.02 | 0.09 | 95.54 | 0.00 | 0.00 | 0.00 | 70.29 | 0.00 | 98.60 | 0.00 | 96.22 | 0.00 | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.473859869 |
| 69.58 | 0.01 | 66.34 | 0.00 | 60.04 | 0.02 | 95.54 | 0.00 | 0.00 | 0.00 | 70.29 | 0.00 | 98.60 | 0.00 | 96.22 | 0.00 | /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.919862975 |
| Name |
|---|
| /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.219804477 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1478558832 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3378074819 |
| /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2867892379 |
| /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3951760130 |
| /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.427864024 |
| /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2075688487 |
| /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.4177395761 |
| /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.514886838 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.865173522 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.587310212 |
| /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3140822742 |
| /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1011865141 |
| /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3454454925 |
| /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.438173447 |
| /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2649453112 |
| /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2911973619 |
| /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.4059039887 |
| /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1503014234 |
| /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3668927314 |
| /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3827532600 |
| /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2428042537 |
| /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1212299439 |
| /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3046087654 |
| /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2152887448 |
| /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.507802936 |
| /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1330958752 |
| /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3867790268 |
| /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2628114462 |
| /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3222275315 |
| /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.17459161 |
| /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.106503176 |
| /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1953775391 |
| /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3302437470 |
| /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1563016768 |
| /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.968432058 |
| /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1831239400 |
| /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1750098221 |
| /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2450850992 |
| /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1831879635 |
| /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3901571396 |
| /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3525050568 |
| /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2676838553 |
| /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1347418132 |
| /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3898510495 |
| /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2708114887 |
| /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.559009489 |
| /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.311055831 |
| /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3005060713 |
| /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1991492703 |
| /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2839968880 |
| /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1158677449 |
| /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1858897551 |
| /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1987900514 |
| /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3763941438 |
| /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2710559191 |
| /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3876651001 |
| /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3667591229 |
| /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.960086786 |
| /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.927339702 |
| /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3193343538 |
| /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1179427220 |
| /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3955237177 |
| /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3911241629 |
| /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.850888924 |
| /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.489762213 |
| /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1099218180 |
| /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2052503742 |
| /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1272133186 |
| /workspace/coverage/cover_reg_top/19.usbdev_intr_test.190730625 |
| /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.175425706 |
| /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.416264712 |
| /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.776715280 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2058751604 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4291959506 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2234627237 |
| /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1585553795 |
| /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3945014031 |
| /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.137125120 |
| /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2702214527 |
| /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2432598429 |
| /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1459154155 |
| /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1795267130 |
| /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2148163185 |
| /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2113785789 |
| /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3585501063 |
| /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1055341900 |
| /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1744547440 |
| /workspace/coverage/cover_reg_top/26.usbdev_intr_test.6570254 |
| /workspace/coverage/cover_reg_top/27.usbdev_intr_test.656494997 |
| /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1053112547 |
| /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2541151829 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.786489813 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4108268744 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2386254618 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2324420211 |
| /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1341868703 |
| /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2692307094 |
| /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4066478040 |
| /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2273482777 |
| /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3937128779 |
| /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.446086900 |
| /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2509413568 |
| /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2942379280 |
| /workspace/coverage/cover_reg_top/31.usbdev_intr_test.461558844 |
| /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1331035985 |
| /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2396959721 |
| /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3254469023 |
| /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2302032814 |
| /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4067591926 |
| /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1885307230 |
| /workspace/coverage/cover_reg_top/39.usbdev_intr_test.705002300 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1020995348 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1450270151 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3700018464 |
| /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.517097165 |
| /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1155782946 |
| /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4027632726 |
| /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3474307974 |
| /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3285835887 |
| /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3486391528 |
| /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1932884557 |
| /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2105657250 |
| /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1154992997 |
| /workspace/coverage/cover_reg_top/42.usbdev_intr_test.533986416 |
| /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3329188601 |
| /workspace/coverage/cover_reg_top/47.usbdev_intr_test.122257360 |
| /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2509195655 |
| /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2076434386 |
| /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2022418730 |
| /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2613640158 |
| /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2005842484 |
| /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1446160013 |
| /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1245139025 |
| /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3479358571 |
| /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3482449511 |
| /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.983191730 |
| /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3170580744 |
| /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1821936838 |
| /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2122935824 |
| /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.232179640 |
| /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2453453263 |
| /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2691008752 |
| /workspace/coverage/cover_reg_top/7.usbdev_intr_test.4231018464 |
| /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2603557593 |
| /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2473496219 |
| /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3390101934 |
| /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.100734836 |
| /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2161657839 |
| /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1880049628 |
| /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.594997243 |
| /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3059647930 |
| /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3294841128 |
| /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1309858138 |
| /workspace/coverage/cover_reg_top/9.usbdev_intr_test.489478655 |
| /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.4192748798 |
| /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4199888333 |
| /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.542287943 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2230011292 | Jul 01 10:34:39 AM PDT 24 | Jul 01 10:34:42 AM PDT 24 | 144359572 ps | ||
| T2 | /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2613640158 | Jul 01 10:34:56 AM PDT 24 | Jul 01 10:34:59 AM PDT 24 | 81308114 ps | ||
| T3 | /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3193343538 | Jul 01 10:34:45 AM PDT 24 | Jul 01 10:34:48 AM PDT 24 | 270160312 ps | ||
| T7 | /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.446086900 | Jul 01 10:34:56 AM PDT 24 | Jul 01 10:35:01 AM PDT 24 | 256386144 ps | ||
| T8 | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4259292063 | Jul 01 10:34:51 AM PDT 24 | Jul 01 10:34:53 AM PDT 24 | 98617461 ps | ||
| T13 | /workspace/coverage/cover_reg_top/42.usbdev_intr_test.533986416 | Jul 01 10:35:01 AM PDT 24 | Jul 01 10:35:06 AM PDT 24 | 74740804 ps | ||
| T14 | /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2082487209 | Jul 01 10:35:01 AM PDT 24 | Jul 01 10:35:06 AM PDT 24 | 48857718 ps | ||
| T20 | /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3474307974 | Jul 01 10:34:41 AM PDT 24 | Jul 01 10:34:46 AM PDT 24 | 204398882 ps | ||
| T21 | /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1245139025 | Jul 01 10:34:55 AM PDT 24 | Jul 01 10:34:59 AM PDT 24 | 191056778 ps | ||
| T15 | /workspace/coverage/cover_reg_top/26.usbdev_intr_test.6570254 | Jul 01 10:34:52 AM PDT 24 | Jul 01 10:34:54 AM PDT 24 | 67755427 ps | ||
| T4 | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.505092259 | Jul 01 10:35:02 AM PDT 24 | Jul 01 10:35:11 AM PDT 24 | 717243965 ps | ||
| T22 | /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.416264712 | Jul 01 10:35:02 AM PDT 24 | Jul 01 10:35:09 AM PDT 24 | 176699258 ps | ||
| T11 | /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2428042537 | Jul 01 10:34:47 AM PDT 24 | Jul 01 10:34:49 AM PDT 24 | 111552374 ps | ||
| T16 | /workspace/coverage/cover_reg_top/47.usbdev_intr_test.122257360 | Jul 01 10:34:56 AM PDT 24 | Jul 01 10:34:59 AM PDT 24 | 87676120 ps | ||
| T19 | /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2450850992 | Jul 01 10:35:01 AM PDT 24 | Jul 01 10:35:12 AM PDT 24 | 37371814 ps | ||
| T46 | /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.4192748798 | Jul 01 10:35:01 AM PDT 24 | Jul 01 10:35:06 AM PDT 24 | 201983133 ps | ||
| T5 | /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2324420211 | Jul 01 10:34:46 AM PDT 24 | Jul 01 10:34:49 AM PDT 24 | 110007334 ps | ||
| T6 | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3775132075 | Jul 01 10:34:41 AM PDT 24 | Jul 01 10:34:43 AM PDT 24 | 185695142 ps | ||
| T37 | /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2161657839 | Jul 01 10:35:04 AM PDT 24 | Jul 01 10:35:11 AM PDT 24 | 59842060 ps | ||
| T31 | /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2058751604 | Jul 01 10:34:32 AM PDT 24 | Jul 01 10:34:36 AM PDT 24 | 303168578 ps | ||
| T38 | /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.983191730 | Jul 01 10:34:59 AM PDT 24 | Jul 01 10:35:03 AM PDT 24 | 54876463 ps | ||
| T30 | /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.4059039887 | Jul 01 10:34:38 AM PDT 24 | Jul 01 10:34:41 AM PDT 24 | 565666792 ps | ||
| T26 | /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3876651001 | Jul 01 10:36:04 AM PDT 24 | Jul 01 10:36:09 AM PDT 24 | 606067105 ps | ||
| T32 | /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1020995348 | Jul 01 10:34:42 AM PDT 24 | Jul 01 10:34:47 AM PDT 24 | 340914667 ps | ||
| T17 | /workspace/coverage/cover_reg_top/9.usbdev_intr_test.489478655 | Jul 01 10:35:02 AM PDT 24 | Jul 01 10:35:07 AM PDT 24 | 39558148 ps | ||
| T27 | /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.542287943 | Jul 01 10:35:00 AM PDT 24 | Jul 01 10:35:08 AM PDT 24 | 1333377852 ps | ||
| T18 | /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4067591926 | Jul 01 10:35:20 AM PDT 24 | Jul 01 10:35:24 AM PDT 24 | 31958771 ps | ||
| T28 | /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.514886838 | Jul 01 10:34:43 AM PDT 24 | Jul 01 10:34:47 AM PDT 24 | 431342047 ps | ||
| T49 | /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1478558832 | Jul 01 10:34:57 AM PDT 24 | Jul 01 10:35:04 AM PDT 24 | 432884161 ps | ||
| T29 | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.232179640 | Jul 01 10:34:36 AM PDT 24 | Jul 01 10:34:39 AM PDT 24 | 541362112 ps | ||
| T33 | /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3873142711 | Jul 01 10:34:40 AM PDT 24 | Jul 01 10:34:42 AM PDT 24 | 79089064 ps | ||
| T70 | /workspace/coverage/cover_reg_top/43.usbdev_intr_test.4227479040 | Jul 01 10:34:59 AM PDT 24 | Jul 01 10:35:02 AM PDT 24 | 39636515 ps | ||
| T23 | /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.137125120 | Jul 01 10:34:41 AM PDT 24 | Jul 01 10:34:43 AM PDT 24 | 109508224 ps | ||
| T47 | /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1446160013 | Jul 01 10:34:41 AM PDT 24 | Jul 01 10:34:44 AM PDT 24 | 301525560 ps | ||
| T62 | /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.968432058 | Jul 01 10:34:57 AM PDT 24 | Jul 01 10:35:02 AM PDT 24 | 374909518 ps | ||
| T63 | /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1795267130 | Jul 01 10:35:02 AM PDT 24 | Jul 01 10:35:07 AM PDT 24 | 32008929 ps | ||
| T24 | /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2867892379 | Jul 01 10:35:02 AM PDT 24 | Jul 01 10:35:08 AM PDT 24 | 191784810 ps | ||
| T67 | /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2035477793 | Jul 01 10:34:55 AM PDT 24 | Jul 01 10:34:58 AM PDT 24 | 45032284 ps | ||
| T34 | /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2432598429 | Jul 01 10:34:45 AM PDT 24 | Jul 01 10:34:48 AM PDT 24 | 175959277 ps | ||
| T35 | /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.4177395761 | Jul 01 10:35:01 AM PDT 24 | Jul 01 10:35:06 AM PDT 24 | 113182296 ps | ||
| T25 | /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1179427220 | Jul 01 10:35:04 AM PDT 24 | Jul 01 10:35:11 AM PDT 24 | 149040421 ps | ||
| T48 | /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1309858138 | Jul 01 10:34:59 AM PDT 24 | Jul 01 10:35:03 AM PDT 24 | 65115220 ps | ||
| T66 | /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3111751106 | Jul 01 10:35:07 AM PDT 24 | Jul 01 10:35:15 AM PDT 24 | 38389033 ps | ||
| T83 | /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2676838553 | Jul 01 10:34:54 AM PDT 24 | Jul 01 10:34:58 AM PDT 24 | 166682176 ps | ||
| T84 | /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.559009489 | Jul 01 10:36:00 AM PDT 24 | Jul 01 10:36:07 AM PDT 24 | 72491555 ps | ||
| T59 | /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.919862975 | Jul 01 10:34:46 AM PDT 24 | Jul 01 10:34:50 AM PDT 24 | 207405525 ps | ||
| T85 | /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1347418132 | Jul 01 10:35:09 AM PDT 24 | Jul 01 10:35:17 AM PDT 24 | 73839762 ps | ||
| T73 | /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2148163185 | Jul 01 10:34:54 AM PDT 24 | Jul 01 10:34:57 AM PDT 24 | 34138568 ps | ||
| T64 | /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1885307230 | Jul 01 10:34:56 AM PDT 24 | Jul 01 10:34:59 AM PDT 24 | 59310934 ps | ||
| T86 | /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2273482777 | Jul 01 10:34:40 AM PDT 24 | Jul 01 10:34:43 AM PDT 24 | 140336849 ps | ||
| T61 | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3486391528 | Jul 01 10:34:58 AM PDT 24 | Jul 01 10:35:03 AM PDT 24 | 211758567 ps | ||
| T65 | /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3170580744 | Jul 01 10:34:41 AM PDT 24 | Jul 01 10:34:48 AM PDT 24 | 69154470 ps | ||
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| T36 | /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1858897551 | Jul 01 10:34:43 AM PDT 24 | Jul 01 10:34:45 AM PDT 24 | 54517535 ps | ||
| T87 | /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4199888333 | Jul 01 10:35:00 AM PDT 24 | Jul 01 10:35:06 AM PDT 24 | 83023270 ps | ||
| T39 | /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4027632726 | Jul 01 10:35:00 AM PDT 24 | Jul 01 10:35:06 AM PDT 24 | 184507077 ps | ||
| T88 | /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3285835887 | Jul 01 10:34:54 AM PDT 24 | Jul 01 10:34:58 AM PDT 24 | 165477906 ps | ||
| T89 | /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3140822742 | Jul 01 10:34:40 AM PDT 24 | Jul 01 10:34:42 AM PDT 24 | 55928714 ps | ||
| T90 | /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2541151829 | Jul 01 10:34:53 AM PDT 24 | Jul 01 10:34:55 AM PDT 24 | 85084892 ps | ||
| T91 | /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3901571396 | Jul 01 10:34:46 AM PDT 24 | Jul 01 10:34:49 AM PDT 24 | 69757325 ps | ||
| T40 | /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3454454925 | Jul 01 10:34:38 AM PDT 24 | Jul 01 10:34:40 AM PDT 24 | 95958571 ps | ||
| T92 | /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.850888924 | Jul 01 10:34:59 AM PDT 24 | Jul 01 10:35:03 AM PDT 24 | 327470204 ps | ||
| T93 | /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1154992997 | Jul 01 10:35:11 AM PDT 24 | Jul 01 10:35:17 AM PDT 24 | 43782192 ps | ||
| T75 | /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3898510495 | Jul 01 10:35:31 AM PDT 24 | Jul 01 10:35:33 AM PDT 24 | 57020147 ps | ||
| T94 | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1563016768 | Jul 01 10:35:02 AM PDT 24 | Jul 01 10:35:09 AM PDT 24 | 112500018 ps | ||
| T41 | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.587310212 | Jul 01 10:34:46 AM PDT 24 | Jul 01 10:34:58 AM PDT 24 | 2099960890 ps | ||
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| T95 | /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.175425706 | Jul 01 10:35:56 AM PDT 24 | Jul 01 10:36:00 AM PDT 24 | 97545928 ps | ||
| T60 | /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2453453263 | Jul 01 10:35:01 AM PDT 24 | Jul 01 10:35:08 AM PDT 24 | 167561387 ps | ||
| T96 | /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2996887726 | Jul 01 10:35:02 AM PDT 24 | Jul 01 10:35:07 AM PDT 24 | 77915559 ps | ||
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| T98 | /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4291959506 | Jul 01 10:34:48 AM PDT 24 | Jul 01 10:34:57 AM PDT 24 | 1510938560 ps | ||
| T9 | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2386254618 | Jul 01 10:34:36 AM PDT 24 | Jul 01 10:34:38 AM PDT 24 | 92309894 ps | ||
| T99 | /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.219804477 | Jul 01 10:34:42 AM PDT 24 | Jul 01 10:34:45 AM PDT 24 | 126531012 ps | ||
| T44 | /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.311055831 | Jul 01 10:35:47 AM PDT 24 | Jul 01 10:35:52 AM PDT 24 | 69142634 ps | ||
| T100 | /workspace/coverage/cover_reg_top/19.usbdev_intr_test.190730625 | Jul 01 10:34:50 AM PDT 24 | Jul 01 10:34:52 AM PDT 24 | 45057659 ps | ||
| T101 | /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1459154155 | Jul 01 10:35:02 AM PDT 24 | Jul 01 10:35:10 AM PDT 24 | 159868859 ps | ||
| T102 | /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2152887448 | Jul 01 10:34:48 AM PDT 24 | Jul 01 10:34:51 AM PDT 24 | 99254239 ps | ||
| T79 | /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2473496219 | Jul 01 10:34:36 AM PDT 24 | Jul 01 10:34:41 AM PDT 24 | 659508807 ps | ||
| T103 | /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1821936838 | Jul 01 10:34:41 AM PDT 24 | Jul 01 10:34:44 AM PDT 24 | 198110173 ps | ||
| T104 | /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.17459161 | Jul 01 10:35:05 AM PDT 24 | Jul 01 10:35:17 AM PDT 24 | 82067587 ps | ||
| T105 | /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2234627237 | Jul 01 10:35:07 AM PDT 24 | Jul 01 10:35:15 AM PDT 24 | 167385369 ps | ||
| T45 | /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.517097165 | Jul 01 10:34:40 AM PDT 24 | Jul 01 10:34:42 AM PDT 24 | 80126986 ps | ||
| T106 | /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1953775391 | Jul 01 10:34:59 AM PDT 24 | Jul 01 10:35:02 AM PDT 24 | 33791915 ps | ||
| T107 | /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1744547440 | Jul 01 10:35:00 AM PDT 24 | Jul 01 10:35:04 AM PDT 24 | 98631841 ps | ||
| T108 | /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1330958752 | Jul 01 10:35:40 AM PDT 24 | Jul 01 10:35:42 AM PDT 24 | 29974125 ps | ||
| T80 | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.311095458 | Jul 01 10:35:52 AM PDT 24 | Jul 01 10:36:00 AM PDT 24 | 900491221 ps | ||
| T109 | /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1831879635 | Jul 01 10:35:09 AM PDT 24 | Jul 01 10:35:18 AM PDT 24 | 402209695 ps | ||
| T43 | /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.865173522 | Jul 01 10:35:05 AM PDT 24 | Jul 01 10:35:14 AM PDT 24 | 92063984 ps | ||
| T76 | /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3329188601 | Jul 01 10:35:06 AM PDT 24 | Jul 01 10:35:14 AM PDT 24 | 72535231 ps | ||
| T110 | /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.100734836 | Jul 01 10:34:58 AM PDT 24 | Jul 01 10:35:02 AM PDT 24 | 71242903 ps | ||
| T111 | /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.489762213 | Jul 01 10:35:35 AM PDT 24 | Jul 01 10:35:39 AM PDT 24 | 271090274 ps | ||
| T112 | /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1932884557 | Jul 01 10:34:59 AM PDT 24 | Jul 01 10:35:07 AM PDT 24 | 737036081 ps | ||
| T113 | /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3911241629 | Jul 01 10:34:53 AM PDT 24 | Jul 01 10:35:01 AM PDT 24 | 40457713 ps | ||
| T114 | /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1055341900 | Jul 01 10:35:06 AM PDT 24 | Jul 01 10:35:13 AM PDT 24 | 40909375 ps | ||
| T115 | /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2113785789 | Jul 01 10:35:37 AM PDT 24 | Jul 01 10:35:40 AM PDT 24 | 44820001 ps | ||
| T116 | /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2710559191 | Jul 01 10:35:08 AM PDT 24 | Jul 01 10:35:17 AM PDT 24 | 177756357 ps | ||
| T117 | /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.427864024 | Jul 01 10:34:52 AM PDT 24 | Jul 01 10:34:55 AM PDT 24 | 56102922 ps | ||
| T118 | /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3585501063 | Jul 01 10:35:45 AM PDT 24 | Jul 01 10:35:47 AM PDT 24 | 102872597 ps | ||
| T77 | /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2105657250 | Jul 01 10:35:01 AM PDT 24 | Jul 01 10:35:05 AM PDT 24 | 50526519 ps | ||
| T119 | /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4066478040 | Jul 01 10:34:52 AM PDT 24 | Jul 01 10:34:56 AM PDT 24 | 205295147 ps | ||
| T120 | /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.927339702 | Jul 01 10:35:39 AM PDT 24 | Jul 01 10:35:41 AM PDT 24 | 76229931 ps | ||
| T121 | /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1212299439 | Jul 01 10:34:53 AM PDT 24 | Jul 01 10:34:56 AM PDT 24 | 164944624 ps | ||
| T122 | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.473859869 | Jul 01 10:34:38 AM PDT 24 | Jul 01 10:34:41 AM PDT 24 | 229271788 ps | ||
| T123 | /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1099218180 | Jul 01 10:34:52 AM PDT 24 | Jul 01 10:34:56 AM PDT 24 | 487104341 ps | ||
| T124 | /workspace/coverage/cover_reg_top/27.usbdev_intr_test.656494997 | Jul 01 10:34:57 AM PDT 24 | Jul 01 10:35:00 AM PDT 24 | 41792365 ps | ||
| T125 | /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.507802936 | Jul 01 10:34:37 AM PDT 24 | Jul 01 10:34:38 AM PDT 24 | 75623922 ps | ||
| T126 | /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2075688487 | Jul 01 10:34:36 AM PDT 24 | Jul 01 10:34:40 AM PDT 24 | 374762510 ps | ||
| T127 | /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2708114887 | Jul 01 10:34:34 AM PDT 24 | Jul 01 10:34:37 AM PDT 24 | 177962719 ps | ||
| T128 | /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3955237177 | Jul 01 10:35:01 AM PDT 24 | Jul 01 10:35:05 AM PDT 24 | 79327938 ps | ||
| T129 | /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3667591229 | Jul 01 10:34:39 AM PDT 24 | Jul 01 10:34:42 AM PDT 24 | 111730428 ps | ||
| T130 | /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3867790268 | Jul 01 10:35:03 AM PDT 24 | Jul 01 10:35:09 AM PDT 24 | 178373416 ps | ||
| T10 | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2315754037 | Jul 01 10:35:02 AM PDT 24 | Jul 01 10:35:08 AM PDT 24 | 101339488 ps | ||
| T12 | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2690364059 | Jul 01 10:34:34 AM PDT 24 | Jul 01 10:34:35 AM PDT 24 | 63800169 ps | ||
| T50 | /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4108268744 | Jul 01 10:34:39 AM PDT 24 | Jul 01 10:34:48 AM PDT 24 | 1877658832 ps | ||
| T51 | /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1158677449 | Jul 01 10:34:42 AM PDT 24 | Jul 01 10:34:45 AM PDT 24 | 136148416 ps | ||
| T52 | /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.960086786 | Jul 01 10:34:56 AM PDT 24 | Jul 01 10:34:59 AM PDT 24 | 91537469 ps | ||
| T53 | /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1880049628 | Jul 01 10:34:58 AM PDT 24 | Jul 01 10:35:02 AM PDT 24 | 140802261 ps | ||
| T54 | /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.776715280 | Jul 01 10:35:29 AM PDT 24 | Jul 01 10:35:32 AM PDT 24 | 471258826 ps | ||
| T55 | /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3294841128 | Jul 01 10:35:02 AM PDT 24 | Jul 01 10:35:09 AM PDT 24 | 184294895 ps | ||
| T56 | /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2691008752 | Jul 01 10:35:03 AM PDT 24 | Jul 01 10:35:10 AM PDT 24 | 151849728 ps | ||
| T57 | /workspace/coverage/cover_reg_top/39.usbdev_intr_test.705002300 | Jul 01 10:35:03 AM PDT 24 | Jul 01 10:35:09 AM PDT 24 | 47836462 ps | ||
| T58 | /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3005060713 | Jul 01 10:35:55 AM PDT 24 | Jul 01 10:36:00 AM PDT 24 | 470048074 ps | ||
| T131 | /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2022418730 | Jul 01 10:34:58 AM PDT 24 | Jul 01 10:35:02 AM PDT 24 | 73104500 ps | ||
| T132 | /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3827532600 | Jul 01 10:34:49 AM PDT 24 | Jul 01 10:34:52 AM PDT 24 | 38822635 ps | ||
| T133 | /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1831239400 | Jul 01 10:34:45 AM PDT 24 | Jul 01 10:34:47 AM PDT 24 | 79497332 ps | ||
| T134 | /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3937128779 | Jul 01 10:34:51 AM PDT 24 | Jul 01 10:34:54 AM PDT 24 | 190770489 ps | ||
| T78 | /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3059647930 | Jul 01 10:34:59 AM PDT 24 | Jul 01 10:35:06 AM PDT 24 | 777520105 ps | ||
| T135 | /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1272133186 | Jul 01 10:34:37 AM PDT 24 | Jul 01 10:34:44 AM PDT 24 | 80762611 ps | ||
| T136 | /workspace/coverage/cover_reg_top/7.usbdev_intr_test.4231018464 | Jul 01 10:34:42 AM PDT 24 | Jul 01 10:34:44 AM PDT 24 | 40058194 ps | ||
| T137 | /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2509195655 | Jul 01 10:35:02 AM PDT 24 | Jul 01 10:35:07 AM PDT 24 | 48622858 ps | ||
| T138 | /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.786489813 | Jul 01 10:34:46 AM PDT 24 | Jul 01 10:34:50 AM PDT 24 | 248720540 ps | ||
| T139 | /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.106503176 | Jul 01 10:35:02 AM PDT 24 | Jul 01 10:35:09 AM PDT 24 | 69712368 ps | ||
| T140 | /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3700018464 | Jul 01 10:34:40 AM PDT 24 | Jul 01 10:34:44 AM PDT 24 | 152458485 ps | ||
| T141 | /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1991492703 | Jul 01 10:35:05 AM PDT 24 | Jul 01 10:35:17 AM PDT 24 | 212983384 ps | ||
| T142 | /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1341868703 | Jul 01 10:34:48 AM PDT 24 | Jul 01 10:34:50 AM PDT 24 | 34132788 ps | ||
| T143 | /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3763941438 | Jul 01 10:35:54 AM PDT 24 | Jul 01 10:35:59 AM PDT 24 | 365689032 ps | ||
| T144 | /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1987900514 | Jul 01 10:34:58 AM PDT 24 | Jul 01 10:35:01 AM PDT 24 | 45585139 ps | ||
| T145 | /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3668927314 | Jul 01 10:34:55 AM PDT 24 | Jul 01 10:34:57 AM PDT 24 | 85088826 ps | ||
| T146 | /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2302032814 | Jul 01 10:35:06 AM PDT 24 | Jul 01 10:35:14 AM PDT 24 | 63441430 ps | ||
| T147 | /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3525050568 | Jul 01 10:35:00 AM PDT 24 | Jul 01 10:35:06 AM PDT 24 | 551936686 ps | ||
| T148 | /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3945014031 | Jul 01 10:34:50 AM PDT 24 | Jul 01 10:34:53 AM PDT 24 | 55728011 ps | ||
| T149 | /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2942379280 | Jul 01 10:35:55 AM PDT 24 | Jul 01 10:35:59 AM PDT 24 | 31165005 ps | ||
| T150 | /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1503014234 | Jul 01 10:34:39 AM PDT 24 | Jul 01 10:34:41 AM PDT 24 | 102446702 ps | ||
| T81 | /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2839968880 | Jul 01 10:34:43 AM PDT 24 | Jul 01 10:34:47 AM PDT 24 | 489970337 ps | ||
| T151 | /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2396959721 | Jul 01 10:34:48 AM PDT 24 | Jul 01 10:34:51 AM PDT 24 | 65703780 ps | ||
| T152 | /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2628114462 | Jul 01 10:34:56 AM PDT 24 | Jul 01 10:35:00 AM PDT 24 | 122399061 ps | ||
| T153 | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3222275315 | Jul 01 10:35:00 AM PDT 24 | Jul 01 10:35:05 AM PDT 24 | 602468887 ps | ||
| T154 | /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1155782946 | Jul 01 10:34:55 AM PDT 24 | Jul 01 10:34:57 AM PDT 24 | 85965723 ps | ||
| T155 | /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2692307094 | Jul 01 10:34:43 AM PDT 24 | Jul 01 10:34:45 AM PDT 24 | 69850430 ps | ||
| T156 | /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2603557593 | Jul 01 10:34:52 AM PDT 24 | Jul 01 10:34:55 AM PDT 24 | 220695273 ps | ||
| T157 | /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3254469023 | Jul 01 10:35:04 AM PDT 24 | Jul 01 10:35:11 AM PDT 24 | 32969726 ps | ||
| T158 | /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3390101934 | Jul 01 10:35:00 AM PDT 24 | Jul 01 10:35:05 AM PDT 24 | 195541073 ps | ||
| T82 | /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3830087472 | Jul 01 10:34:52 AM PDT 24 | Jul 01 10:34:57 AM PDT 24 | 658667279 ps | ||
| T159 | /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2509413568 | Jul 01 10:34:37 AM PDT 24 | Jul 01 10:34:40 AM PDT 24 | 957716938 ps | ||
| T160 | /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2076434386 | Jul 01 10:35:01 AM PDT 24 | Jul 01 10:35:06 AM PDT 24 | 45406094 ps | ||
| T161 | /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2702214527 | Jul 01 10:34:51 AM PDT 24 | Jul 01 10:34:55 AM PDT 24 | 103808761 ps | ||
| T162 | /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3302437470 | Jul 01 10:34:48 AM PDT 24 | Jul 01 10:34:52 AM PDT 24 | 210652161 ps | ||
| T163 | /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1750098221 | Jul 01 10:34:44 AM PDT 24 | Jul 01 10:34:46 AM PDT 24 | 57467020 ps | ||
| T164 | /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3046087654 | Jul 01 10:34:40 AM PDT 24 | Jul 01 10:34:44 AM PDT 24 | 400574448 ps | ||
| T165 | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2911973619 | Jul 01 10:34:44 AM PDT 24 | Jul 01 10:34:48 AM PDT 24 | 305732748 ps | ||
| T166 | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3479358571 | Jul 01 10:35:36 AM PDT 24 | Jul 01 10:35:40 AM PDT 24 | 677727807 ps | ||
| T167 | /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1450270151 | Jul 01 10:34:57 AM PDT 24 | Jul 01 10:35:04 AM PDT 24 | 906384403 ps | ||
| T168 | /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2052503742 | Jul 01 10:35:09 AM PDT 24 | Jul 01 10:35:18 AM PDT 24 | 127304734 ps | ||
| T169 | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3378074819 | Jul 01 10:34:48 AM PDT 24 | Jul 01 10:34:50 AM PDT 24 | 67169466 ps | ||
| T170 | /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3482449511 | Jul 01 10:35:02 AM PDT 24 | Jul 01 10:35:09 AM PDT 24 | 165112490 ps | ||
| T171 | /workspace/coverage/cover_reg_top/31.usbdev_intr_test.461558844 | Jul 01 10:34:56 AM PDT 24 | Jul 01 10:34:59 AM PDT 24 | 57923599 ps | ||
| T172 | /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2122935824 | Jul 01 10:34:41 AM PDT 24 | Jul 01 10:34:44 AM PDT 24 | 160875337 ps | ||
| T173 | /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2649453112 | Jul 01 10:34:41 AM PDT 24 | Jul 01 10:34:43 AM PDT 24 | 126431921 ps | ||
| T174 | /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.438173447 | Jul 01 10:34:41 AM PDT 24 | Jul 01 10:34:45 AM PDT 24 | 387424783 ps | ||
| T175 | /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.594997243 | Jul 01 10:35:05 AM PDT 24 | Jul 01 10:35:16 AM PDT 24 | 132843208 ps |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.4259292063 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 98617461 ps |
| CPU time | 1.02 seconds |
| Started | Jul 01 10:34:51 AM PDT 24 |
| Finished | Jul 01 10:34:53 AM PDT 24 |
| Peak memory | 205880 kb |
| Host | smart-25417c9b-d88b-4345-8344-e61621d16986 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4259292063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.4259292063 |
| Directory | /workspace/14.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/38.usbdev_intr_test.2082487209 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 48857718 ps |
| CPU time | 0.68 seconds |
| Started | Jul 01 10:35:01 AM PDT 24 |
| Finished | Jul 01 10:35:06 AM PDT 24 |
| Peak memory | 205696 kb |
| Host | smart-48165647-36e5-4fab-a189-f600a912f0d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2082487209 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.2082487209 |
| Directory | /workspace/38.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.2230011292 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 144359572 ps |
| CPU time | 3.07 seconds |
| Started | Jul 01 10:34:39 AM PDT 24 |
| Finished | Jul 01 10:34:42 AM PDT 24 |
| Peak memory | 205892 kb |
| Host | smart-836488cb-1e17-4114-bcac-575f13965db4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2230011292 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.2230011292 |
| Directory | /workspace/7.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2690364059 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 63800169 ps |
| CPU time | 0.78 seconds |
| Started | Jul 01 10:34:34 AM PDT 24 |
| Finished | Jul 01 10:34:35 AM PDT 24 |
| Peak memory | 205784 kb |
| Host | smart-3e24a9b1-0043-4518-9f41-9b98e7bc79a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2690364059 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2690364059 |
| Directory | /workspace/1.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.usbdev_intr_test.3111751106 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 38389033 ps |
| CPU time | 0.65 seconds |
| Started | Jul 01 10:35:07 AM PDT 24 |
| Finished | Jul 01 10:35:15 AM PDT 24 |
| Peak memory | 205680 kb |
| Host | smart-3d0cc78b-aa96-45ac-8d5a-0c924d2afee8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3111751106 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.3111751106 |
| Directory | /workspace/44.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.505092259 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 717243965 ps |
| CPU time | 4.43 seconds |
| Started | Jul 01 10:35:02 AM PDT 24 |
| Finished | Jul 01 10:35:11 AM PDT 24 |
| Peak memory | 205896 kb |
| Host | smart-c86ad932-d560-4147-ae53-2f527c40249e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=505092259 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.505092259 |
| Directory | /workspace/17.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.3775132075 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 185695142 ps |
| CPU time | 0.86 seconds |
| Started | Jul 01 10:34:41 AM PDT 24 |
| Finished | Jul 01 10:34:43 AM PDT 24 |
| Peak memory | 205800 kb |
| Host | smart-a3241a5d-5ad3-40f1-8947-7953ecb20145 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3775132075 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.3775132075 |
| Directory | /workspace/4.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.usbdev_intr_test.4227479040 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 39636515 ps |
| CPU time | 0.67 seconds |
| Started | Jul 01 10:34:59 AM PDT 24 |
| Finished | Jul 01 10:35:02 AM PDT 24 |
| Peak memory | 205688 kb |
| Host | smart-c6ca0f62-a8a5-4c15-9a23-072353574f31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4227479040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.4227479040 |
| Directory | /workspace/43.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/46.usbdev_intr_test.2996887726 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 77915559 ps |
| CPU time | 0.71 seconds |
| Started | Jul 01 10:35:02 AM PDT 24 |
| Finished | Jul 01 10:35:07 AM PDT 24 |
| Peak memory | 205700 kb |
| Host | smart-fb431bd3-2790-4888-b6f1-b68338a3d8cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2996887726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.2996887726 |
| Directory | /workspace/46.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2035477793 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 45032284 ps |
| CPU time | 0.69 seconds |
| Started | Jul 01 10:34:55 AM PDT 24 |
| Finished | Jul 01 10:34:58 AM PDT 24 |
| Peak memory | 205648 kb |
| Host | smart-2094ffed-04da-48ae-92dd-224cc835d132 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2035477793 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2035477793 |
| Directory | /workspace/15.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.3830087472 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 658667279 ps |
| CPU time | 4.09 seconds |
| Started | Jul 01 10:34:52 AM PDT 24 |
| Finished | Jul 01 10:34:57 AM PDT 24 |
| Peak memory | 205940 kb |
| Host | smart-319adc64-fa16-4b7d-a24a-250d75b01c48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3830087472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.3830087472 |
| Directory | /workspace/2.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_intr_test.2688518944 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 62197048 ps |
| CPU time | 0.77 seconds |
| Started | Jul 01 10:34:52 AM PDT 24 |
| Finished | Jul 01 10:34:54 AM PDT 24 |
| Peak memory | 205680 kb |
| Host | smart-54742e4d-9b3a-4674-9684-d8b5d955fa94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2688518944 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.2688518944 |
| Directory | /workspace/17.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3873142711 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 79089064 ps |
| CPU time | 1.07 seconds |
| Started | Jul 01 10:34:40 AM PDT 24 |
| Finished | Jul 01 10:34:42 AM PDT 24 |
| Peak memory | 206212 kb |
| Host | smart-d81909ac-4a5a-4acd-b2d7-54bf319bed48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3873142711 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3873142711 |
| Directory | /workspace/0.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.311095458 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 900491221 ps |
| CPU time | 5.36 seconds |
| Started | Jul 01 10:35:52 AM PDT 24 |
| Finished | Jul 01 10:36:00 AM PDT 24 |
| Peak memory | 206056 kb |
| Host | smart-d5e554da-7b08-428e-b20d-ccd765b8d4c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=311095458 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.311095458 |
| Directory | /workspace/14.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.2315754037 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 101339488 ps |
| CPU time | 0.9 seconds |
| Started | Jul 01 10:35:02 AM PDT 24 |
| Finished | Jul 01 10:35:08 AM PDT 24 |
| Peak memory | 205804 kb |
| Host | smart-cda23ef7-a5e2-4bf4-92be-1003f5c7dfaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2315754037 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.2315754037 |
| Directory | /workspace/2.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.473859869 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 229271788 ps |
| CPU time | 2.24 seconds |
| Started | Jul 01 10:34:38 AM PDT 24 |
| Finished | Jul 01 10:34:41 AM PDT 24 |
| Peak memory | 222036 kb |
| Host | smart-9cbed7a7-71a4-4f8a-ad1d-c37cb6a37064 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=473859869 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.473859869 |
| Directory | /workspace/0.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.919862975 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 207405525 ps |
| CPU time | 2.1 seconds |
| Started | Jul 01 10:34:46 AM PDT 24 |
| Finished | Jul 01 10:34:50 AM PDT 24 |
| Peak memory | 214132 kb |
| Host | smart-42db063c-6b78-4269-bd13-91ad18e4e0df |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919862975 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev _csr_mem_rw_with_rand_reset.919862975 |
| Directory | /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.219804477 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 126531012 ps |
| CPU time | 1.87 seconds |
| Started | Jul 01 10:34:42 AM PDT 24 |
| Finished | Jul 01 10:34:45 AM PDT 24 |
| Peak memory | 205916 kb |
| Host | smart-2ad1b298-f467-42db-a41a-3038ecef338f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=219804477 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.219804477 |
| Directory | /workspace/0.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1478558832 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 432884161 ps |
| CPU time | 3.89 seconds |
| Started | Jul 01 10:34:57 AM PDT 24 |
| Finished | Jul 01 10:35:04 AM PDT 24 |
| Peak memory | 205948 kb |
| Host | smart-7f6d86a8-2a43-46ed-a83e-ec4fecf7d95f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1478558832 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1478558832 |
| Directory | /workspace/0.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.3378074819 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 67169466 ps |
| CPU time | 0.8 seconds |
| Started | Jul 01 10:34:48 AM PDT 24 |
| Finished | Jul 01 10:34:50 AM PDT 24 |
| Peak memory | 205800 kb |
| Host | smart-53d2e3e3-4210-4ccd-ac31-473438368f2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3378074819 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.3378074819 |
| Directory | /workspace/0.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.2867892379 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 191784810 ps |
| CPU time | 1.77 seconds |
| Started | Jul 01 10:35:02 AM PDT 24 |
| Finished | Jul 01 10:35:08 AM PDT 24 |
| Peak memory | 222272 kb |
| Host | smart-48467147-ea08-4ef7-a433-f56d2547d89b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867892379 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde v_csr_mem_rw_with_rand_reset.2867892379 |
| Directory | /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_intr_test.3951760130 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 75466402 ps |
| CPU time | 0.7 seconds |
| Started | Jul 01 10:34:40 AM PDT 24 |
| Finished | Jul 01 10:34:42 AM PDT 24 |
| Peak memory | 205736 kb |
| Host | smart-637620f4-cca8-4c6b-aa81-54e527998534 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3951760130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.3951760130 |
| Directory | /workspace/0.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.427864024 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 56102922 ps |
| CPU time | 1.33 seconds |
| Started | Jul 01 10:34:52 AM PDT 24 |
| Finished | Jul 01 10:34:55 AM PDT 24 |
| Peak memory | 222180 kb |
| Host | smart-a0d108ba-0318-4847-ade2-2553223e1b16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=427864024 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.427864024 |
| Directory | /workspace/0.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.2075688487 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 374762510 ps |
| CPU time | 2.61 seconds |
| Started | Jul 01 10:34:36 AM PDT 24 |
| Finished | Jul 01 10:34:40 AM PDT 24 |
| Peak memory | 205808 kb |
| Host | smart-49f25428-3897-44ee-aaa2-2f98293d7f4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2075688487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.2075688487 |
| Directory | /workspace/0.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.4177395761 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 113182296 ps |
| CPU time | 1.15 seconds |
| Started | Jul 01 10:35:01 AM PDT 24 |
| Finished | Jul 01 10:35:06 AM PDT 24 |
| Peak memory | 205876 kb |
| Host | smart-b06fb341-b5ba-499b-b141-454eee044412 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4177395761 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.4177395761 |
| Directory | /workspace/0.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.514886838 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 431342047 ps |
| CPU time | 2.58 seconds |
| Started | Jul 01 10:34:43 AM PDT 24 |
| Finished | Jul 01 10:34:47 AM PDT 24 |
| Peak memory | 205920 kb |
| Host | smart-9242f9bf-e9ff-41b3-ba35-b0b492efdb2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=514886838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.514886838 |
| Directory | /workspace/0.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.865173522 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 92063984 ps |
| CPU time | 1.95 seconds |
| Started | Jul 01 10:35:05 AM PDT 24 |
| Finished | Jul 01 10:35:14 AM PDT 24 |
| Peak memory | 205840 kb |
| Host | smart-680bc6fb-38a3-4dca-840e-db113284f396 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=865173522 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.865173522 |
| Directory | /workspace/1.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.587310212 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 2099960890 ps |
| CPU time | 10.27 seconds |
| Started | Jul 01 10:34:46 AM PDT 24 |
| Finished | Jul 01 10:34:58 AM PDT 24 |
| Peak memory | 205872 kb |
| Host | smart-a9fcbffb-749e-4df5-bddc-55fefe08c0d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=587310212 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.587310212 |
| Directory | /workspace/1.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.3140822742 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 55928714 ps |
| CPU time | 0.84 seconds |
| Started | Jul 01 10:34:40 AM PDT 24 |
| Finished | Jul 01 10:34:42 AM PDT 24 |
| Peak memory | 205772 kb |
| Host | smart-2a178aa8-9445-4700-9156-003676a09cb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3140822742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.3140822742 |
| Directory | /workspace/1.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1011865141 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 36813868 ps |
| CPU time | 0.65 seconds |
| Started | Jul 01 10:35:02 AM PDT 24 |
| Finished | Jul 01 10:35:07 AM PDT 24 |
| Peak memory | 205732 kb |
| Host | smart-e96dcd83-40c1-4b0e-8ea8-0006164088f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1011865141 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1011865141 |
| Directory | /workspace/1.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.3454454925 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 95958571 ps |
| CPU time | 1.42 seconds |
| Started | Jul 01 10:34:38 AM PDT 24 |
| Finished | Jul 01 10:34:40 AM PDT 24 |
| Peak memory | 214140 kb |
| Host | smart-f75bcfa0-575a-41a3-b640-e263b84490e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3454454925 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.3454454925 |
| Directory | /workspace/1.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.438173447 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 387424783 ps |
| CPU time | 2.68 seconds |
| Started | Jul 01 10:34:41 AM PDT 24 |
| Finished | Jul 01 10:34:45 AM PDT 24 |
| Peak memory | 205852 kb |
| Host | smart-ce3f6824-fb61-477e-9169-d0e8756fd452 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=438173447 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.438173447 |
| Directory | /workspace/1.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2649453112 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 126431921 ps |
| CPU time | 1.1 seconds |
| Started | Jul 01 10:34:41 AM PDT 24 |
| Finished | Jul 01 10:34:43 AM PDT 24 |
| Peak memory | 205872 kb |
| Host | smart-d7b1ef02-50a7-4749-a738-2aaf3ff13bf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2649453112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2649453112 |
| Directory | /workspace/1.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.2911973619 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 305732748 ps |
| CPU time | 3.12 seconds |
| Started | Jul 01 10:34:44 AM PDT 24 |
| Finished | Jul 01 10:34:48 AM PDT 24 |
| Peak memory | 206056 kb |
| Host | smart-e5c50186-12ff-4932-a880-4ae833faa815 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2911973619 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.2911973619 |
| Directory | /workspace/1.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.4059039887 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 565666792 ps |
| CPU time | 2.6 seconds |
| Started | Jul 01 10:34:38 AM PDT 24 |
| Finished | Jul 01 10:34:41 AM PDT 24 |
| Peak memory | 205920 kb |
| Host | smart-6257eb34-12a6-45da-ae8a-2c797a4d0894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=4059039887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.4059039887 |
| Directory | /workspace/1.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.1503014234 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 102446702 ps |
| CPU time | 1.19 seconds |
| Started | Jul 01 10:34:39 AM PDT 24 |
| Finished | Jul 01 10:34:41 AM PDT 24 |
| Peak memory | 214160 kb |
| Host | smart-6fc6c6ef-0218-4f86-9ffa-61712f52afcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503014234 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd ev_csr_mem_rw_with_rand_reset.1503014234 |
| Directory | /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.3668927314 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 85088826 ps |
| CPU time | 1.04 seconds |
| Started | Jul 01 10:34:55 AM PDT 24 |
| Finished | Jul 01 10:34:57 AM PDT 24 |
| Peak memory | 205852 kb |
| Host | smart-638a9b14-bd43-4e20-8f46-b872e5df691f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3668927314 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.3668927314 |
| Directory | /workspace/10.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_intr_test.3827532600 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 38822635 ps |
| CPU time | 0.77 seconds |
| Started | Jul 01 10:34:49 AM PDT 24 |
| Finished | Jul 01 10:34:52 AM PDT 24 |
| Peak memory | 205708 kb |
| Host | smart-9e52d205-0153-4925-a1ce-7ee9c8acd3fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3827532600 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.3827532600 |
| Directory | /workspace/10.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2428042537 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 111552374 ps |
| CPU time | 1.21 seconds |
| Started | Jul 01 10:34:47 AM PDT 24 |
| Finished | Jul 01 10:34:49 AM PDT 24 |
| Peak memory | 205952 kb |
| Host | smart-76b248a2-f83e-4036-820e-dcb6ad63263e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2428042537 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2428042537 |
| Directory | /workspace/10.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.1212299439 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 164944624 ps |
| CPU time | 1.81 seconds |
| Started | Jul 01 10:34:53 AM PDT 24 |
| Finished | Jul 01 10:34:56 AM PDT 24 |
| Peak memory | 221624 kb |
| Host | smart-3ee43b9a-6758-4f68-baed-512c3c3315d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1212299439 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.1212299439 |
| Directory | /workspace/10.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.3046087654 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 400574448 ps |
| CPU time | 2.73 seconds |
| Started | Jul 01 10:34:40 AM PDT 24 |
| Finished | Jul 01 10:34:44 AM PDT 24 |
| Peak memory | 205864 kb |
| Host | smart-9a61cdf4-3802-4a08-83b0-4df138111205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3046087654 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.3046087654 |
| Directory | /workspace/10.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.2152887448 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 99254239 ps |
| CPU time | 1.36 seconds |
| Started | Jul 01 10:34:48 AM PDT 24 |
| Finished | Jul 01 10:34:51 AM PDT 24 |
| Peak memory | 214136 kb |
| Host | smart-7194118f-f150-4517-a006-620cf7cf2620 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152887448 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd ev_csr_mem_rw_with_rand_reset.2152887448 |
| Directory | /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.507802936 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 75623922 ps |
| CPU time | 0.97 seconds |
| Started | Jul 01 10:34:37 AM PDT 24 |
| Finished | Jul 01 10:34:38 AM PDT 24 |
| Peak memory | 205932 kb |
| Host | smart-4652c3c4-e5ce-4678-983a-564c0880bf69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=507802936 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.507802936 |
| Directory | /workspace/11.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_intr_test.1330958752 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 29974125 ps |
| CPU time | 0.72 seconds |
| Started | Jul 01 10:35:40 AM PDT 24 |
| Finished | Jul 01 10:35:42 AM PDT 24 |
| Peak memory | 205676 kb |
| Host | smart-02f8fc5d-0d34-49cd-a70d-8278afcc9ef6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1330958752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.1330958752 |
| Directory | /workspace/11.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3867790268 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 178373416 ps |
| CPU time | 1.25 seconds |
| Started | Jul 01 10:35:03 AM PDT 24 |
| Finished | Jul 01 10:35:09 AM PDT 24 |
| Peak memory | 205964 kb |
| Host | smart-a7667072-6d08-441a-9e45-976742b060af |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3867790268 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3867790268 |
| Directory | /workspace/11.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.2628114462 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 122399061 ps |
| CPU time | 1.64 seconds |
| Started | Jul 01 10:34:56 AM PDT 24 |
| Finished | Jul 01 10:35:00 AM PDT 24 |
| Peak memory | 205904 kb |
| Host | smart-d93e23ef-df08-4563-a5e1-420a524d0f82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2628114462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.2628114462 |
| Directory | /workspace/11.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.3222275315 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 602468887 ps |
| CPU time | 2.88 seconds |
| Started | Jul 01 10:35:00 AM PDT 24 |
| Finished | Jul 01 10:35:05 AM PDT 24 |
| Peak memory | 205868 kb |
| Host | smart-f89cfebb-6ae4-4f95-9ceb-3babcabdfc65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3222275315 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.3222275315 |
| Directory | /workspace/11.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.17459161 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 82067587 ps |
| CPU time | 1.56 seconds |
| Started | Jul 01 10:35:05 AM PDT 24 |
| Finished | Jul 01 10:35:17 AM PDT 24 |
| Peak memory | 214292 kb |
| Host | smart-72763412-73eb-48dc-9f00-9a24a8e1c503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17459161 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=u sbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev _csr_mem_rw_with_rand_reset.17459161 |
| Directory | /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.106503176 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 69712368 ps |
| CPU time | 0.85 seconds |
| Started | Jul 01 10:35:02 AM PDT 24 |
| Finished | Jul 01 10:35:09 AM PDT 24 |
| Peak memory | 205804 kb |
| Host | smart-f1e5dfcb-34f9-45fb-8e21-d73a87ffbd88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=106503176 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.106503176 |
| Directory | /workspace/12.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1953775391 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 33791915 ps |
| CPU time | 0.64 seconds |
| Started | Jul 01 10:34:59 AM PDT 24 |
| Finished | Jul 01 10:35:02 AM PDT 24 |
| Peak memory | 205696 kb |
| Host | smart-f31c93d0-b6fe-49c2-9047-0812e5e412f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1953775391 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1953775391 |
| Directory | /workspace/12.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.3302437470 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 210652161 ps |
| CPU time | 1.66 seconds |
| Started | Jul 01 10:34:48 AM PDT 24 |
| Finished | Jul 01 10:34:52 AM PDT 24 |
| Peak memory | 205892 kb |
| Host | smart-c62aa469-4f8f-4bb2-9bc4-8014e1e1dc0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3302437470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.3302437470 |
| Directory | /workspace/12.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.1563016768 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 112500018 ps |
| CPU time | 2.47 seconds |
| Started | Jul 01 10:35:02 AM PDT 24 |
| Finished | Jul 01 10:35:09 AM PDT 24 |
| Peak memory | 221764 kb |
| Host | smart-dc698360-ffd2-404a-9247-6730618fbbd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1563016768 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.1563016768 |
| Directory | /workspace/12.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.968432058 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 374909518 ps |
| CPU time | 2.73 seconds |
| Started | Jul 01 10:34:57 AM PDT 24 |
| Finished | Jul 01 10:35:02 AM PDT 24 |
| Peak memory | 205956 kb |
| Host | smart-82aaae0b-076e-4e4d-92c9-709350cf7cfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=968432058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.968432058 |
| Directory | /workspace/12.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.1831239400 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 79497332 ps |
| CPU time | 1.15 seconds |
| Started | Jul 01 10:34:45 AM PDT 24 |
| Finished | Jul 01 10:34:47 AM PDT 24 |
| Peak memory | 214148 kb |
| Host | smart-f1d2a051-cc70-4d2f-b3c5-26d4e16f1a68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831239400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbd ev_csr_mem_rw_with_rand_reset.1831239400 |
| Directory | /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.1750098221 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 57467020 ps |
| CPU time | 1.04 seconds |
| Started | Jul 01 10:34:44 AM PDT 24 |
| Finished | Jul 01 10:34:46 AM PDT 24 |
| Peak memory | 206152 kb |
| Host | smart-f22778b9-5b79-442e-904f-878080cd4688 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1750098221 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.1750098221 |
| Directory | /workspace/13.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_intr_test.2450850992 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 37371814 ps |
| CPU time | 0.68 seconds |
| Started | Jul 01 10:35:01 AM PDT 24 |
| Finished | Jul 01 10:35:12 AM PDT 24 |
| Peak memory | 205692 kb |
| Host | smart-41bf36a3-8643-413b-b9aa-f1627bdf67c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2450850992 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.2450850992 |
| Directory | /workspace/13.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.1831879635 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 402209695 ps |
| CPU time | 2.08 seconds |
| Started | Jul 01 10:35:09 AM PDT 24 |
| Finished | Jul 01 10:35:18 AM PDT 24 |
| Peak memory | 205952 kb |
| Host | smart-0ea46d3b-dbc6-4626-a01a-307816a0bc5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1831879635 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.1831879635 |
| Directory | /workspace/13.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.3901571396 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 69757325 ps |
| CPU time | 1.82 seconds |
| Started | Jul 01 10:34:46 AM PDT 24 |
| Finished | Jul 01 10:34:49 AM PDT 24 |
| Peak memory | 205936 kb |
| Host | smart-7590794e-29f2-49ba-bc1e-722a785464f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3901571396 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.3901571396 |
| Directory | /workspace/13.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.3525050568 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 551936686 ps |
| CPU time | 2.89 seconds |
| Started | Jul 01 10:35:00 AM PDT 24 |
| Finished | Jul 01 10:35:06 AM PDT 24 |
| Peak memory | 205852 kb |
| Host | smart-b4237da6-d3b8-4cd2-b6d2-6c4771f7e547 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3525050568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.3525050568 |
| Directory | /workspace/13.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.2676838553 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 166682176 ps |
| CPU time | 2.02 seconds |
| Started | Jul 01 10:34:54 AM PDT 24 |
| Finished | Jul 01 10:34:58 AM PDT 24 |
| Peak memory | 214136 kb |
| Host | smart-b6b45784-40c3-4569-980a-b17380d61fe4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676838553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd ev_csr_mem_rw_with_rand_reset.2676838553 |
| Directory | /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1347418132 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 73839762 ps |
| CPU time | 0.9 seconds |
| Started | Jul 01 10:35:09 AM PDT 24 |
| Finished | Jul 01 10:35:17 AM PDT 24 |
| Peak memory | 205760 kb |
| Host | smart-9e71d1ff-8416-4cea-a151-bd38955dd80d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1347418132 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1347418132 |
| Directory | /workspace/14.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_intr_test.3898510495 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 57020147 ps |
| CPU time | 0.73 seconds |
| Started | Jul 01 10:35:31 AM PDT 24 |
| Finished | Jul 01 10:35:33 AM PDT 24 |
| Peak memory | 205708 kb |
| Host | smart-43621be2-208f-47f9-b384-1c092f50e17e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3898510495 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.3898510495 |
| Directory | /workspace/14.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.2708114887 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 177962719 ps |
| CPU time | 1.89 seconds |
| Started | Jul 01 10:34:34 AM PDT 24 |
| Finished | Jul 01 10:34:37 AM PDT 24 |
| Peak memory | 205928 kb |
| Host | smart-07d8df97-58e9-4cc0-8dcb-27f01a2058a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2708114887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.2708114887 |
| Directory | /workspace/14.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.559009489 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 72491555 ps |
| CPU time | 1.49 seconds |
| Started | Jul 01 10:36:00 AM PDT 24 |
| Finished | Jul 01 10:36:07 AM PDT 24 |
| Peak memory | 214128 kb |
| Host | smart-81d25002-ca26-4dd7-91fd-2820f8c3d901 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559009489 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ= usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbde v_csr_mem_rw_with_rand_reset.559009489 |
| Directory | /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.311055831 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 69142634 ps |
| CPU time | 1.05 seconds |
| Started | Jul 01 10:35:47 AM PDT 24 |
| Finished | Jul 01 10:35:52 AM PDT 24 |
| Peak memory | 205956 kb |
| Host | smart-2df2bdad-1d57-432a-b3ec-25c82155c98e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=311055831 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.311055831 |
| Directory | /workspace/15.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3005060713 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 470048074 ps |
| CPU time | 2.07 seconds |
| Started | Jul 01 10:35:55 AM PDT 24 |
| Finished | Jul 01 10:36:00 AM PDT 24 |
| Peak memory | 205904 kb |
| Host | smart-4d2eea01-c939-4ee7-b222-deefb63f2750 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3005060713 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3005060713 |
| Directory | /workspace/15.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.1991492703 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 212983384 ps |
| CPU time | 1.89 seconds |
| Started | Jul 01 10:35:05 AM PDT 24 |
| Finished | Jul 01 10:35:17 AM PDT 24 |
| Peak memory | 221816 kb |
| Host | smart-ff294490-d9a0-4b8b-81ec-e1b921411f3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1991492703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.1991492703 |
| Directory | /workspace/15.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.2839968880 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 489970337 ps |
| CPU time | 2.95 seconds |
| Started | Jul 01 10:34:43 AM PDT 24 |
| Finished | Jul 01 10:34:47 AM PDT 24 |
| Peak memory | 205864 kb |
| Host | smart-ce894690-516b-4230-8e6c-7ac5b2885536 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2839968880 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.2839968880 |
| Directory | /workspace/15.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.1158677449 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 136148416 ps |
| CPU time | 1.6 seconds |
| Started | Jul 01 10:34:42 AM PDT 24 |
| Finished | Jul 01 10:34:45 AM PDT 24 |
| Peak memory | 217848 kb |
| Host | smart-3a84d5b2-d0bb-4f02-813a-8a230c4099c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158677449 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd ev_csr_mem_rw_with_rand_reset.1158677449 |
| Directory | /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.1858897551 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 54517535 ps |
| CPU time | 0.79 seconds |
| Started | Jul 01 10:34:43 AM PDT 24 |
| Finished | Jul 01 10:34:45 AM PDT 24 |
| Peak memory | 205760 kb |
| Host | smart-88476738-8dee-4931-8ae9-5914fee1709e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1858897551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.1858897551 |
| Directory | /workspace/16.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1987900514 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 45585139 ps |
| CPU time | 0.72 seconds |
| Started | Jul 01 10:34:58 AM PDT 24 |
| Finished | Jul 01 10:35:01 AM PDT 24 |
| Peak memory | 205688 kb |
| Host | smart-f82205c1-3de6-499b-b48f-1eee9d1e6ec7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1987900514 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1987900514 |
| Directory | /workspace/16.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.3763941438 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 365689032 ps |
| CPU time | 1.34 seconds |
| Started | Jul 01 10:35:54 AM PDT 24 |
| Finished | Jul 01 10:35:59 AM PDT 24 |
| Peak memory | 205960 kb |
| Host | smart-9a2c4d8f-564b-4bd2-addf-ccf86fc98472 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3763941438 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.3763941438 |
| Directory | /workspace/16.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2710559191 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 177756357 ps |
| CPU time | 2.07 seconds |
| Started | Jul 01 10:35:08 AM PDT 24 |
| Finished | Jul 01 10:35:17 AM PDT 24 |
| Peak memory | 215196 kb |
| Host | smart-14ffbbeb-43a0-42ce-b85a-98498c45d6ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2710559191 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2710559191 |
| Directory | /workspace/16.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.3876651001 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 606067105 ps |
| CPU time | 2.9 seconds |
| Started | Jul 01 10:36:04 AM PDT 24 |
| Finished | Jul 01 10:36:09 AM PDT 24 |
| Peak memory | 205924 kb |
| Host | smart-aaec5d34-a7f3-4c75-adb5-0fa7df96b5bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3876651001 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.3876651001 |
| Directory | /workspace/16.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.3667591229 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 111730428 ps |
| CPU time | 2.56 seconds |
| Started | Jul 01 10:34:39 AM PDT 24 |
| Finished | Jul 01 10:34:42 AM PDT 24 |
| Peak memory | 214168 kb |
| Host | smart-7ec4054c-1c73-4003-ac50-b56f5a535941 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667591229 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd ev_csr_mem_rw_with_rand_reset.3667591229 |
| Directory | /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.960086786 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 91537469 ps |
| CPU time | 0.99 seconds |
| Started | Jul 01 10:34:56 AM PDT 24 |
| Finished | Jul 01 10:34:59 AM PDT 24 |
| Peak memory | 205932 kb |
| Host | smart-f654b38d-ec05-4fce-95c5-bf82908a6c96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=960086786 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.960086786 |
| Directory | /workspace/17.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.927339702 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 76229931 ps |
| CPU time | 1.1 seconds |
| Started | Jul 01 10:35:39 AM PDT 24 |
| Finished | Jul 01 10:35:41 AM PDT 24 |
| Peak memory | 205832 kb |
| Host | smart-06858f0d-f552-4ebc-b3f8-01c6dd5222b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=927339702 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.927339702 |
| Directory | /workspace/17.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.3193343538 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 270160312 ps |
| CPU time | 2.76 seconds |
| Started | Jul 01 10:34:45 AM PDT 24 |
| Finished | Jul 01 10:34:48 AM PDT 24 |
| Peak memory | 205988 kb |
| Host | smart-845049ee-caa0-423a-ad81-c02b6a0878e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3193343538 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.3193343538 |
| Directory | /workspace/17.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.1179427220 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 149040421 ps |
| CPU time | 1.25 seconds |
| Started | Jul 01 10:35:04 AM PDT 24 |
| Finished | Jul 01 10:35:11 AM PDT 24 |
| Peak memory | 214192 kb |
| Host | smart-664041f5-d869-41e4-8f1a-50a6e7d7f0d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179427220 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd ev_csr_mem_rw_with_rand_reset.1179427220 |
| Directory | /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3955237177 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 79327938 ps |
| CPU time | 1.04 seconds |
| Started | Jul 01 10:35:01 AM PDT 24 |
| Finished | Jul 01 10:35:05 AM PDT 24 |
| Peak memory | 205840 kb |
| Host | smart-156b1271-4fb1-430e-b244-b5637ded0aba |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=3955237177 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3955237177 |
| Directory | /workspace/18.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_intr_test.3911241629 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 40457713 ps |
| CPU time | 0.67 seconds |
| Started | Jul 01 10:34:53 AM PDT 24 |
| Finished | Jul 01 10:35:01 AM PDT 24 |
| Peak memory | 205688 kb |
| Host | smart-ee29f708-da1a-46c5-b34f-fa69f105459a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3911241629 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.3911241629 |
| Directory | /workspace/18.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.850888924 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 327470204 ps |
| CPU time | 1.86 seconds |
| Started | Jul 01 10:34:59 AM PDT 24 |
| Finished | Jul 01 10:35:03 AM PDT 24 |
| Peak memory | 205928 kb |
| Host | smart-ad240f2f-491a-48a3-9a06-3810e3a2adc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=850888924 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.850888924 |
| Directory | /workspace/18.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.489762213 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 271090274 ps |
| CPU time | 2.95 seconds |
| Started | Jul 01 10:35:35 AM PDT 24 |
| Finished | Jul 01 10:35:39 AM PDT 24 |
| Peak memory | 222220 kb |
| Host | smart-808c8ee8-6eea-4858-ab8f-42b005a0529b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=489762213 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.489762213 |
| Directory | /workspace/18.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.1099218180 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 487104341 ps |
| CPU time | 2.59 seconds |
| Started | Jul 01 10:34:52 AM PDT 24 |
| Finished | Jul 01 10:34:56 AM PDT 24 |
| Peak memory | 205844 kb |
| Host | smart-f0ac1b21-2582-433b-81a4-3b970502231a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1099218180 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.1099218180 |
| Directory | /workspace/18.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.2052503742 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 127304734 ps |
| CPU time | 2.25 seconds |
| Started | Jul 01 10:35:09 AM PDT 24 |
| Finished | Jul 01 10:35:18 AM PDT 24 |
| Peak memory | 214136 kb |
| Host | smart-b3b9fc37-6a28-4577-8c4a-904b397352b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052503742 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbd ev_csr_mem_rw_with_rand_reset.2052503742 |
| Directory | /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1272133186 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 80762611 ps |
| CPU time | 0.84 seconds |
| Started | Jul 01 10:34:37 AM PDT 24 |
| Finished | Jul 01 10:34:44 AM PDT 24 |
| Peak memory | 205764 kb |
| Host | smart-7bc7d3b5-8fe9-4061-ac28-379f0455d365 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1272133186 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1272133186 |
| Directory | /workspace/19.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_intr_test.190730625 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 45057659 ps |
| CPU time | 0.68 seconds |
| Started | Jul 01 10:34:50 AM PDT 24 |
| Finished | Jul 01 10:34:52 AM PDT 24 |
| Peak memory | 205732 kb |
| Host | smart-5677d1f4-1fff-4d60-bb85-8a12669ef1af |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=190730625 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.190730625 |
| Directory | /workspace/19.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.175425706 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 97545928 ps |
| CPU time | 1.12 seconds |
| Started | Jul 01 10:35:56 AM PDT 24 |
| Finished | Jul 01 10:36:00 AM PDT 24 |
| Peak memory | 205944 kb |
| Host | smart-91ef7f14-888d-45ad-89bc-024261778a0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=175425706 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.175425706 |
| Directory | /workspace/19.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.416264712 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 176699258 ps |
| CPU time | 2.27 seconds |
| Started | Jul 01 10:35:02 AM PDT 24 |
| Finished | Jul 01 10:35:09 AM PDT 24 |
| Peak memory | 214180 kb |
| Host | smart-6f948f80-7dc0-4278-904c-45b727bbd9d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=416264712 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.416264712 |
| Directory | /workspace/19.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.776715280 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 471258826 ps |
| CPU time | 2.79 seconds |
| Started | Jul 01 10:35:29 AM PDT 24 |
| Finished | Jul 01 10:35:32 AM PDT 24 |
| Peak memory | 205936 kb |
| Host | smart-90df763d-38ab-464e-9688-c23c9d9d8d7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=776715280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.776715280 |
| Directory | /workspace/19.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.2058751604 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 303168578 ps |
| CPU time | 3.49 seconds |
| Started | Jul 01 10:34:32 AM PDT 24 |
| Finished | Jul 01 10:34:36 AM PDT 24 |
| Peak memory | 205920 kb |
| Host | smart-5d49ee2a-721a-41ba-8d47-6ec786818ce1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2058751604 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.2058751604 |
| Directory | /workspace/2.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.4291959506 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 1510938560 ps |
| CPU time | 7.88 seconds |
| Started | Jul 01 10:34:48 AM PDT 24 |
| Finished | Jul 01 10:34:57 AM PDT 24 |
| Peak memory | 205884 kb |
| Host | smart-99c005ae-d864-46a7-a31c-c7c2cec971af |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4291959506 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.4291959506 |
| Directory | /workspace/2.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2234627237 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 167385369 ps |
| CPU time | 1.24 seconds |
| Started | Jul 01 10:35:07 AM PDT 24 |
| Finished | Jul 01 10:35:15 AM PDT 24 |
| Peak memory | 214252 kb |
| Host | smart-87c3a10b-a5b7-4ff9-af84-5cf09d59c185 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234627237 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde v_csr_mem_rw_with_rand_reset.2234627237 |
| Directory | /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.1585553795 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 70850044 ps |
| CPU time | 0.92 seconds |
| Started | Jul 01 10:34:33 AM PDT 24 |
| Finished | Jul 01 10:34:34 AM PDT 24 |
| Peak memory | 205868 kb |
| Host | smart-9c00b51b-b24a-4b3a-93a8-8ff8dc49e073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1585553795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.1585553795 |
| Directory | /workspace/2.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_intr_test.3945014031 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 55728011 ps |
| CPU time | 0.8 seconds |
| Started | Jul 01 10:34:50 AM PDT 24 |
| Finished | Jul 01 10:34:53 AM PDT 24 |
| Peak memory | 205728 kb |
| Host | smart-674109b9-40fe-4be0-a324-ba96075ee701 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3945014031 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.3945014031 |
| Directory | /workspace/2.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.137125120 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 109508224 ps |
| CPU time | 1.41 seconds |
| Started | Jul 01 10:34:41 AM PDT 24 |
| Finished | Jul 01 10:34:43 AM PDT 24 |
| Peak memory | 214096 kb |
| Host | smart-6996e110-ad9f-4f13-b733-64d93b2bef34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=137125120 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.137125120 |
| Directory | /workspace/2.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.2702214527 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 103808761 ps |
| CPU time | 2.47 seconds |
| Started | Jul 01 10:34:51 AM PDT 24 |
| Finished | Jul 01 10:34:55 AM PDT 24 |
| Peak memory | 205880 kb |
| Host | smart-f247243a-c20c-4ec2-8a0e-05765c02fe55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2702214527 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.2702214527 |
| Directory | /workspace/2.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.2432598429 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 175959277 ps |
| CPU time | 1.63 seconds |
| Started | Jul 01 10:34:45 AM PDT 24 |
| Finished | Jul 01 10:34:48 AM PDT 24 |
| Peak memory | 205916 kb |
| Host | smart-a7c68145-caec-43cd-a830-8b960aa7193e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2432598429 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.2432598429 |
| Directory | /workspace/2.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.1459154155 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 159868859 ps |
| CPU time | 1.83 seconds |
| Started | Jul 01 10:35:02 AM PDT 24 |
| Finished | Jul 01 10:35:10 AM PDT 24 |
| Peak memory | 205964 kb |
| Host | smart-fd181830-6077-4b0e-9e54-2f07c7f1bacd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1459154155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.1459154155 |
| Directory | /workspace/2.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1795267130 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 32008929 ps |
| CPU time | 0.66 seconds |
| Started | Jul 01 10:35:02 AM PDT 24 |
| Finished | Jul 01 10:35:07 AM PDT 24 |
| Peak memory | 205700 kb |
| Host | smart-1ecdfb0d-97ae-432b-90e1-4f711ff413a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1795267130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1795267130 |
| Directory | /workspace/20.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/21.usbdev_intr_test.2148163185 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 34138568 ps |
| CPU time | 0.64 seconds |
| Started | Jul 01 10:34:54 AM PDT 24 |
| Finished | Jul 01 10:34:57 AM PDT 24 |
| Peak memory | 205732 kb |
| Host | smart-00747e40-463e-4c71-aa73-f491bd5c086c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2148163185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.2148163185 |
| Directory | /workspace/21.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2113785789 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 44820001 ps |
| CPU time | 0.72 seconds |
| Started | Jul 01 10:35:37 AM PDT 24 |
| Finished | Jul 01 10:35:40 AM PDT 24 |
| Peak memory | 205676 kb |
| Host | smart-b29c14b4-eda4-427a-b5d1-05e5cb8a8903 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2113785789 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2113785789 |
| Directory | /workspace/22.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/23.usbdev_intr_test.3585501063 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 102872597 ps |
| CPU time | 0.73 seconds |
| Started | Jul 01 10:35:45 AM PDT 24 |
| Finished | Jul 01 10:35:47 AM PDT 24 |
| Peak memory | 205680 kb |
| Host | smart-165e75ce-805e-4e97-9938-4c905abca5be |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3585501063 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.3585501063 |
| Directory | /workspace/23.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/24.usbdev_intr_test.1055341900 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 40909375 ps |
| CPU time | 0.66 seconds |
| Started | Jul 01 10:35:06 AM PDT 24 |
| Finished | Jul 01 10:35:13 AM PDT 24 |
| Peak memory | 205700 kb |
| Host | smart-e432873d-27b0-4294-810e-3cfe4743ecf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1055341900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.1055341900 |
| Directory | /workspace/24.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/25.usbdev_intr_test.1744547440 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 98631841 ps |
| CPU time | 0.69 seconds |
| Started | Jul 01 10:35:00 AM PDT 24 |
| Finished | Jul 01 10:35:04 AM PDT 24 |
| Peak memory | 205704 kb |
| Host | smart-44bd7c3c-40d3-4c9a-a4b8-1b207c532a9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1744547440 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.1744547440 |
| Directory | /workspace/25.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/26.usbdev_intr_test.6570254 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 67755427 ps |
| CPU time | 0.72 seconds |
| Started | Jul 01 10:34:52 AM PDT 24 |
| Finished | Jul 01 10:34:54 AM PDT 24 |
| Peak memory | 205584 kb |
| Host | smart-df69a2ca-a66e-4ddf-836b-31cfc89cabb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=6570254 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.6570254 |
| Directory | /workspace/26.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/27.usbdev_intr_test.656494997 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 41792365 ps |
| CPU time | 0.71 seconds |
| Started | Jul 01 10:34:57 AM PDT 24 |
| Finished | Jul 01 10:35:00 AM PDT 24 |
| Peak memory | 205596 kb |
| Host | smart-efbed8cf-a0e4-42bb-999f-d717fa349ec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=656494997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.656494997 |
| Directory | /workspace/27.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1053112547 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 59776765 ps |
| CPU time | 0.65 seconds |
| Started | Jul 01 10:35:15 AM PDT 24 |
| Finished | Jul 01 10:35:21 AM PDT 24 |
| Peak memory | 205696 kb |
| Host | smart-6df3bc16-fe7b-418f-b6ae-041925d57387 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1053112547 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1053112547 |
| Directory | /workspace/28.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/29.usbdev_intr_test.2541151829 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 85084892 ps |
| CPU time | 0.77 seconds |
| Started | Jul 01 10:34:53 AM PDT 24 |
| Finished | Jul 01 10:34:55 AM PDT 24 |
| Peak memory | 205688 kb |
| Host | smart-ef7317e4-1cb2-420f-848e-457961973974 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2541151829 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.2541151829 |
| Directory | /workspace/29.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.786489813 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 248720540 ps |
| CPU time | 2.12 seconds |
| Started | Jul 01 10:34:46 AM PDT 24 |
| Finished | Jul 01 10:34:50 AM PDT 24 |
| Peak memory | 205968 kb |
| Host | smart-15f17781-7d76-4253-b722-200b62658aff |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=786489813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.786489813 |
| Directory | /workspace/3.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.4108268744 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 1877658832 ps |
| CPU time | 8.47 seconds |
| Started | Jul 01 10:34:39 AM PDT 24 |
| Finished | Jul 01 10:34:48 AM PDT 24 |
| Peak memory | 205900 kb |
| Host | smart-e1cb5eb8-9470-43d6-ab9e-64368471424d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=4108268744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.4108268744 |
| Directory | /workspace/3.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.2386254618 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 92309894 ps |
| CPU time | 0.94 seconds |
| Started | Jul 01 10:34:36 AM PDT 24 |
| Finished | Jul 01 10:34:38 AM PDT 24 |
| Peak memory | 205828 kb |
| Host | smart-8ade96d4-1bbe-47ee-9264-60cef95452da |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2386254618 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.2386254618 |
| Directory | /workspace/3.usbdev_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2324420211 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 110007334 ps |
| CPU time | 1.93 seconds |
| Started | Jul 01 10:34:46 AM PDT 24 |
| Finished | Jul 01 10:34:49 AM PDT 24 |
| Peak memory | 222576 kb |
| Host | smart-48bc6a45-821b-4acb-bc11-1a6af15e3949 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324420211 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde v_csr_mem_rw_with_rand_reset.2324420211 |
| Directory | /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.1341868703 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 34132788 ps |
| CPU time | 0.85 seconds |
| Started | Jul 01 10:34:48 AM PDT 24 |
| Finished | Jul 01 10:34:50 AM PDT 24 |
| Peak memory | 205752 kb |
| Host | smart-6956d85d-a2e1-4a2d-93a8-3945d1199f72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1341868703 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.1341868703 |
| Directory | /workspace/3.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2692307094 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 69850430 ps |
| CPU time | 0.69 seconds |
| Started | Jul 01 10:34:43 AM PDT 24 |
| Finished | Jul 01 10:34:45 AM PDT 24 |
| Peak memory | 205708 kb |
| Host | smart-684ba65b-db22-42d2-9270-9721088eedf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2692307094 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.2692307094 |
| Directory | /workspace/3.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.4066478040 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 205295147 ps |
| CPU time | 2.37 seconds |
| Started | Jul 01 10:34:52 AM PDT 24 |
| Finished | Jul 01 10:34:56 AM PDT 24 |
| Peak memory | 215096 kb |
| Host | smart-ef8ed282-38a4-4f61-a3d4-6da5fd797706 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4066478040 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.4066478040 |
| Directory | /workspace/3.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2273482777 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 140336849 ps |
| CPU time | 2.24 seconds |
| Started | Jul 01 10:34:40 AM PDT 24 |
| Finished | Jul 01 10:34:43 AM PDT 24 |
| Peak memory | 205892 kb |
| Host | smart-0c5b5cf6-bff6-49e9-b868-36a481b42831 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=2273482777 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2273482777 |
| Directory | /workspace/3.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.3937128779 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 190770489 ps |
| CPU time | 1.71 seconds |
| Started | Jul 01 10:34:51 AM PDT 24 |
| Finished | Jul 01 10:34:54 AM PDT 24 |
| Peak memory | 205856 kb |
| Host | smart-59fcc3c6-91cb-4ed7-979a-c6f93bbdbb55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3937128779 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.3937128779 |
| Directory | /workspace/3.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.446086900 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 256386144 ps |
| CPU time | 2.74 seconds |
| Started | Jul 01 10:34:56 AM PDT 24 |
| Finished | Jul 01 10:35:01 AM PDT 24 |
| Peak memory | 214324 kb |
| Host | smart-0bcfbf6c-4d74-4a6f-859b-6515ee3331b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=446086900 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.446086900 |
| Directory | /workspace/3.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.2509413568 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 957716938 ps |
| CPU time | 2.97 seconds |
| Started | Jul 01 10:34:37 AM PDT 24 |
| Finished | Jul 01 10:34:40 AM PDT 24 |
| Peak memory | 205952 kb |
| Host | smart-aeb77e6e-1e79-427a-8f61-1bbbd8c0412f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2509413568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.2509413568 |
| Directory | /workspace/3.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/30.usbdev_intr_test.2942379280 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 31165005 ps |
| CPU time | 0.65 seconds |
| Started | Jul 01 10:35:55 AM PDT 24 |
| Finished | Jul 01 10:35:59 AM PDT 24 |
| Peak memory | 205684 kb |
| Host | smart-ec31e0fc-cd45-4086-9436-e4634788d4c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2942379280 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.2942379280 |
| Directory | /workspace/30.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/31.usbdev_intr_test.461558844 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 57923599 ps |
| CPU time | 0.7 seconds |
| Started | Jul 01 10:34:56 AM PDT 24 |
| Finished | Jul 01 10:34:59 AM PDT 24 |
| Peak memory | 205716 kb |
| Host | smart-9aa9ae94-2853-4134-86ad-39e47ca41335 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=461558844 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.461558844 |
| Directory | /workspace/31.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/32.usbdev_intr_test.1331035985 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 54891315 ps |
| CPU time | 0.69 seconds |
| Started | Jul 01 10:35:03 AM PDT 24 |
| Finished | Jul 01 10:35:12 AM PDT 24 |
| Peak memory | 205688 kb |
| Host | smart-eeeefc42-ae4b-4d24-a4e6-6dd937b594c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1331035985 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.1331035985 |
| Directory | /workspace/32.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/33.usbdev_intr_test.2396959721 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 65703780 ps |
| CPU time | 0.7 seconds |
| Started | Jul 01 10:34:48 AM PDT 24 |
| Finished | Jul 01 10:34:51 AM PDT 24 |
| Peak memory | 205652 kb |
| Host | smart-d0e7c5ee-4b37-48e0-8894-ebeae58eff82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2396959721 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.2396959721 |
| Directory | /workspace/33.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/34.usbdev_intr_test.3254469023 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 32969726 ps |
| CPU time | 0.66 seconds |
| Started | Jul 01 10:35:04 AM PDT 24 |
| Finished | Jul 01 10:35:11 AM PDT 24 |
| Peak memory | 205708 kb |
| Host | smart-55ae2159-0f0f-41da-945b-5d0459256361 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3254469023 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.3254469023 |
| Directory | /workspace/34.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/35.usbdev_intr_test.2302032814 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 63441430 ps |
| CPU time | 0.7 seconds |
| Started | Jul 01 10:35:06 AM PDT 24 |
| Finished | Jul 01 10:35:14 AM PDT 24 |
| Peak memory | 205680 kb |
| Host | smart-e1abac90-737a-4de5-9a71-7bace5e9a4c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2302032814 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.2302032814 |
| Directory | /workspace/35.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/36.usbdev_intr_test.4067591926 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 31958771 ps |
| CPU time | 0.71 seconds |
| Started | Jul 01 10:35:20 AM PDT 24 |
| Finished | Jul 01 10:35:24 AM PDT 24 |
| Peak memory | 205676 kb |
| Host | smart-d1337093-35fd-4af5-8742-cb0deb2685ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4067591926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.4067591926 |
| Directory | /workspace/36.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/37.usbdev_intr_test.1885307230 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 59310934 ps |
| CPU time | 0.71 seconds |
| Started | Jul 01 10:34:56 AM PDT 24 |
| Finished | Jul 01 10:34:59 AM PDT 24 |
| Peak memory | 205700 kb |
| Host | smart-5f1076f3-6d91-480b-b8a4-eedc9b5a87c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1885307230 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.1885307230 |
| Directory | /workspace/37.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/39.usbdev_intr_test.705002300 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 47836462 ps |
| CPU time | 0.7 seconds |
| Started | Jul 01 10:35:03 AM PDT 24 |
| Finished | Jul 01 10:35:09 AM PDT 24 |
| Peak memory | 205708 kb |
| Host | smart-03f58a3a-0eea-4fef-a703-3910b070296c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=705002300 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.705002300 |
| Directory | /workspace/39.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.1020995348 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 340914667 ps |
| CPU time | 3.62 seconds |
| Started | Jul 01 10:34:42 AM PDT 24 |
| Finished | Jul 01 10:34:47 AM PDT 24 |
| Peak memory | 205936 kb |
| Host | smart-1eedf250-4e98-44ae-97af-9dee144cc8fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1020995348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.1020995348 |
| Directory | /workspace/4.usbdev_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1450270151 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 906384403 ps |
| CPU time | 4.43 seconds |
| Started | Jul 01 10:34:57 AM PDT 24 |
| Finished | Jul 01 10:35:04 AM PDT 24 |
| Peak memory | 205896 kb |
| Host | smart-4a7e01bf-ed97-44a7-8fcc-eacb9c1dee5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1450270151 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1450270151 |
| Directory | /workspace/4.usbdev_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.3700018464 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 152458485 ps |
| CPU time | 1.91 seconds |
| Started | Jul 01 10:34:40 AM PDT 24 |
| Finished | Jul 01 10:34:44 AM PDT 24 |
| Peak memory | 214172 kb |
| Host | smart-e1bbb93f-550d-4b70-9b7a-860cbded5abe |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700018464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbde v_csr_mem_rw_with_rand_reset.3700018464 |
| Directory | /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.517097165 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 80126986 ps |
| CPU time | 1.01 seconds |
| Started | Jul 01 10:34:40 AM PDT 24 |
| Finished | Jul 01 10:34:42 AM PDT 24 |
| Peak memory | 205952 kb |
| Host | smart-4d78323b-188b-457e-ac4d-ba026389ea36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=517097165 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.517097165 |
| Directory | /workspace/4.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_intr_test.1155782946 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 85965723 ps |
| CPU time | 0.7 seconds |
| Started | Jul 01 10:34:55 AM PDT 24 |
| Finished | Jul 01 10:34:57 AM PDT 24 |
| Peak memory | 205732 kb |
| Host | smart-7dc78e3f-1014-4446-adc3-de59c6abccc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1155782946 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.1155782946 |
| Directory | /workspace/4.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4027632726 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 184507077 ps |
| CPU time | 2.23 seconds |
| Started | Jul 01 10:35:00 AM PDT 24 |
| Finished | Jul 01 10:35:06 AM PDT 24 |
| Peak memory | 214144 kb |
| Host | smart-358da7cc-5256-4ac6-b1a0-cb3b1064a68d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4027632726 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.4027632726 |
| Directory | /workspace/4.usbdev_mem_partial_access/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.3474307974 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 204398882 ps |
| CPU time | 4.09 seconds |
| Started | Jul 01 10:34:41 AM PDT 24 |
| Finished | Jul 01 10:34:46 AM PDT 24 |
| Peak memory | 205816 kb |
| Host | smart-2592f235-e76d-4bcd-afaf-bd9ecd0d94c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3474307974 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.3474307974 |
| Directory | /workspace/4.usbdev_mem_walk/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.3285835887 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 165477906 ps |
| CPU time | 1.17 seconds |
| Started | Jul 01 10:34:54 AM PDT 24 |
| Finished | Jul 01 10:34:58 AM PDT 24 |
| Peak memory | 205916 kb |
| Host | smart-12dc22c5-d2bd-46f1-ab5e-c3e33935ada1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=3285835887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.3285835887 |
| Directory | /workspace/4.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.3486391528 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 211758567 ps |
| CPU time | 1.9 seconds |
| Started | Jul 01 10:34:58 AM PDT 24 |
| Finished | Jul 01 10:35:03 AM PDT 24 |
| Peak memory | 214192 kb |
| Host | smart-1684882e-a59a-4287-b54d-9a2d59d980a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3486391528 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.3486391528 |
| Directory | /workspace/4.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.1932884557 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 737036081 ps |
| CPU time | 4.81 seconds |
| Started | Jul 01 10:34:59 AM PDT 24 |
| Finished | Jul 01 10:35:07 AM PDT 24 |
| Peak memory | 205864 kb |
| Host | smart-c7ba4576-86b7-41d1-81e8-c7cef453cb0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=1932884557 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.1932884557 |
| Directory | /workspace/4.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2105657250 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 50526519 ps |
| CPU time | 0.72 seconds |
| Started | Jul 01 10:35:01 AM PDT 24 |
| Finished | Jul 01 10:35:05 AM PDT 24 |
| Peak memory | 205696 kb |
| Host | smart-6f1ec87e-22c4-4df7-8377-ce21d22602a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2105657250 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2105657250 |
| Directory | /workspace/40.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1154992997 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 43782192 ps |
| CPU time | 0.66 seconds |
| Started | Jul 01 10:35:11 AM PDT 24 |
| Finished | Jul 01 10:35:17 AM PDT 24 |
| Peak memory | 205664 kb |
| Host | smart-242f4e4f-8515-4424-a518-d80534910de5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1154992997 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1154992997 |
| Directory | /workspace/41.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/42.usbdev_intr_test.533986416 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 74740804 ps |
| CPU time | 0.72 seconds |
| Started | Jul 01 10:35:01 AM PDT 24 |
| Finished | Jul 01 10:35:06 AM PDT 24 |
| Peak memory | 205708 kb |
| Host | smart-ed1e5d87-be71-4e0b-9c75-a6be81b7e108 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=533986416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.533986416 |
| Directory | /workspace/42.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/45.usbdev_intr_test.3329188601 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 72535231 ps |
| CPU time | 0.69 seconds |
| Started | Jul 01 10:35:06 AM PDT 24 |
| Finished | Jul 01 10:35:14 AM PDT 24 |
| Peak memory | 205700 kb |
| Host | smart-dd50a015-89c7-49be-b3d9-bfb7ad01e8cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3329188601 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.3329188601 |
| Directory | /workspace/45.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/47.usbdev_intr_test.122257360 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 87676120 ps |
| CPU time | 0.81 seconds |
| Started | Jul 01 10:34:56 AM PDT 24 |
| Finished | Jul 01 10:34:59 AM PDT 24 |
| Peak memory | 205704 kb |
| Host | smart-3b1d127a-72a2-43af-ad91-a45e24bb2939 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=122257360 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.122257360 |
| Directory | /workspace/47.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2509195655 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 48622858 ps |
| CPU time | 0.67 seconds |
| Started | Jul 01 10:35:02 AM PDT 24 |
| Finished | Jul 01 10:35:07 AM PDT 24 |
| Peak memory | 205700 kb |
| Host | smart-8375749c-b20f-4715-8a86-063006c18481 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2509195655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2509195655 |
| Directory | /workspace/48.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/49.usbdev_intr_test.2076434386 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 45406094 ps |
| CPU time | 0.68 seconds |
| Started | Jul 01 10:35:01 AM PDT 24 |
| Finished | Jul 01 10:35:06 AM PDT 24 |
| Peak memory | 205740 kb |
| Host | smart-ce7ae90a-352f-410f-ad38-249413811875 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2076434386 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.2076434386 |
| Directory | /workspace/49.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2022418730 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 73104500 ps |
| CPU time | 1.45 seconds |
| Started | Jul 01 10:34:58 AM PDT 24 |
| Finished | Jul 01 10:35:02 AM PDT 24 |
| Peak memory | 214160 kb |
| Host | smart-127876b6-2897-46e9-8e97-b02be4935193 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022418730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde v_csr_mem_rw_with_rand_reset.2022418730 |
| Directory | /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.2613640158 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 81308114 ps |
| CPU time | 1.02 seconds |
| Started | Jul 01 10:34:56 AM PDT 24 |
| Finished | Jul 01 10:34:59 AM PDT 24 |
| Peak memory | 205884 kb |
| Host | smart-7fe17e48-505b-410a-ad60-fa02dfd6e9e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2613640158 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.2613640158 |
| Directory | /workspace/5.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_intr_test.2005842484 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 41000836 ps |
| CPU time | 0.67 seconds |
| Started | Jul 01 10:34:51 AM PDT 24 |
| Finished | Jul 01 10:34:53 AM PDT 24 |
| Peak memory | 205728 kb |
| Host | smart-9b3873da-f926-4183-9014-e2b03d08777d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2005842484 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.2005842484 |
| Directory | /workspace/5.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.1446160013 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 301525560 ps |
| CPU time | 1.62 seconds |
| Started | Jul 01 10:34:41 AM PDT 24 |
| Finished | Jul 01 10:34:44 AM PDT 24 |
| Peak memory | 205916 kb |
| Host | smart-dc1ce829-867a-42a5-ae16-888ec785b510 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1446160013 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.1446160013 |
| Directory | /workspace/5.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.1245139025 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 191056778 ps |
| CPU time | 2.12 seconds |
| Started | Jul 01 10:34:55 AM PDT 24 |
| Finished | Jul 01 10:34:59 AM PDT 24 |
| Peak memory | 221984 kb |
| Host | smart-33210e28-4eca-4053-a576-4c8a6028bd5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1245139025 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.1245139025 |
| Directory | /workspace/5.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3479358571 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 677727807 ps |
| CPU time | 3.01 seconds |
| Started | Jul 01 10:35:36 AM PDT 24 |
| Finished | Jul 01 10:35:40 AM PDT 24 |
| Peak memory | 205916 kb |
| Host | smart-b47e223a-4ec8-4f46-9fd4-273d41cdb2d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3479358571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3479358571 |
| Directory | /workspace/5.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3482449511 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 165112490 ps |
| CPU time | 1.85 seconds |
| Started | Jul 01 10:35:02 AM PDT 24 |
| Finished | Jul 01 10:35:09 AM PDT 24 |
| Peak memory | 222276 kb |
| Host | smart-b7d7a1e4-d7e9-4350-b64d-764a8dbe5449 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482449511 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde v_csr_mem_rw_with_rand_reset.3482449511 |
| Directory | /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.983191730 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 54876463 ps |
| CPU time | 0.82 seconds |
| Started | Jul 01 10:34:59 AM PDT 24 |
| Finished | Jul 01 10:35:03 AM PDT 24 |
| Peak memory | 205828 kb |
| Host | smart-f7b0d610-09d7-4bb0-b2f0-3e7b1269a9c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=983191730 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.983191730 |
| Directory | /workspace/6.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3170580744 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 69154470 ps |
| CPU time | 0.67 seconds |
| Started | Jul 01 10:34:41 AM PDT 24 |
| Finished | Jul 01 10:34:48 AM PDT 24 |
| Peak memory | 205720 kb |
| Host | smart-e6579195-d131-49ce-8f6e-32e8cb142559 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3170580744 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3170580744 |
| Directory | /workspace/6.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.1821936838 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 198110173 ps |
| CPU time | 1.69 seconds |
| Started | Jul 01 10:34:41 AM PDT 24 |
| Finished | Jul 01 10:34:44 AM PDT 24 |
| Peak memory | 205928 kb |
| Host | smart-5f2d43fe-bc22-451e-8555-27a43fc75e69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1821936838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.1821936838 |
| Directory | /workspace/6.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2122935824 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 160875337 ps |
| CPU time | 1.8 seconds |
| Started | Jul 01 10:34:41 AM PDT 24 |
| Finished | Jul 01 10:34:44 AM PDT 24 |
| Peak memory | 214200 kb |
| Host | smart-f9518b9c-bb18-4180-a8e5-119e734a583f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2122935824 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2122935824 |
| Directory | /workspace/6.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.232179640 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 541362112 ps |
| CPU time | 2.96 seconds |
| Started | Jul 01 10:34:36 AM PDT 24 |
| Finished | Jul 01 10:34:39 AM PDT 24 |
| Peak memory | 205932 kb |
| Host | smart-8de0202b-1a6c-469f-b5e8-de5034eda48d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=232179640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.232179640 |
| Directory | /workspace/6.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.2453453263 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 167561387 ps |
| CPU time | 2.56 seconds |
| Started | Jul 01 10:35:01 AM PDT 24 |
| Finished | Jul 01 10:35:08 AM PDT 24 |
| Peak memory | 214196 kb |
| Host | smart-839ff180-9208-43d7-a5c1-ebda6f256306 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453453263 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde v_csr_mem_rw_with_rand_reset.2453453263 |
| Directory | /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.2691008752 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 151849728 ps |
| CPU time | 1.17 seconds |
| Started | Jul 01 10:35:03 AM PDT 24 |
| Finished | Jul 01 10:35:10 AM PDT 24 |
| Peak memory | 206072 kb |
| Host | smart-0374f337-f702-42ca-b5dc-5ceee7f7465f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=2691008752 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.2691008752 |
| Directory | /workspace/7.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_intr_test.4231018464 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 40058194 ps |
| CPU time | 0.64 seconds |
| Started | Jul 01 10:34:42 AM PDT 24 |
| Finished | Jul 01 10:34:44 AM PDT 24 |
| Peak memory | 205728 kb |
| Host | smart-43cd3666-4ebf-48f4-9813-89d008735c47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4231018464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.4231018464 |
| Directory | /workspace/7.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.2603557593 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 220695273 ps |
| CPU time | 1.72 seconds |
| Started | Jul 01 10:34:52 AM PDT 24 |
| Finished | Jul 01 10:34:55 AM PDT 24 |
| Peak memory | 205892 kb |
| Host | smart-7266f838-3596-4d6d-8759-04a8c25f71c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=2603557593 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.2603557593 |
| Directory | /workspace/7.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.2473496219 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 659508807 ps |
| CPU time | 4.41 seconds |
| Started | Jul 01 10:34:36 AM PDT 24 |
| Finished | Jul 01 10:34:41 AM PDT 24 |
| Peak memory | 205956 kb |
| Host | smart-c6faaa83-555f-4272-879c-517f797cff07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=2473496219 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.2473496219 |
| Directory | /workspace/7.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.3390101934 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 195541073 ps |
| CPU time | 1.7 seconds |
| Started | Jul 01 10:35:00 AM PDT 24 |
| Finished | Jul 01 10:35:05 AM PDT 24 |
| Peak memory | 214132 kb |
| Host | smart-37cb9e30-362d-411d-b7fb-bddd5552a886 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390101934 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde v_csr_mem_rw_with_rand_reset.3390101934 |
| Directory | /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.100734836 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 71242903 ps |
| CPU time | 0.99 seconds |
| Started | Jul 01 10:34:58 AM PDT 24 |
| Finished | Jul 01 10:35:02 AM PDT 24 |
| Peak memory | 205904 kb |
| Host | smart-e0561319-1b0c-4b7a-a3e1-bf7f69b790c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=100734836 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.100734836 |
| Directory | /workspace/8.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_intr_test.2161657839 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 59842060 ps |
| CPU time | 0.66 seconds |
| Started | Jul 01 10:35:04 AM PDT 24 |
| Finished | Jul 01 10:35:11 AM PDT 24 |
| Peak memory | 205688 kb |
| Host | smart-6cb0a5df-ee7c-41af-9d70-bde0a45ef0ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2161657839 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.2161657839 |
| Directory | /workspace/8.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.1880049628 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 140802261 ps |
| CPU time | 1.53 seconds |
| Started | Jul 01 10:34:58 AM PDT 24 |
| Finished | Jul 01 10:35:02 AM PDT 24 |
| Peak memory | 205884 kb |
| Host | smart-0b0ab343-6ffb-4803-a817-a9d57f150747 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=1880049628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.1880049628 |
| Directory | /workspace/8.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.594997243 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 132843208 ps |
| CPU time | 3.34 seconds |
| Started | Jul 01 10:35:05 AM PDT 24 |
| Finished | Jul 01 10:35:16 AM PDT 24 |
| Peak memory | 222084 kb |
| Host | smart-e0b5c01c-d939-4969-9e3e-11462130fee6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=594997243 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.594997243 |
| Directory | /workspace/8.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.3059647930 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 777520105 ps |
| CPU time | 4.11 seconds |
| Started | Jul 01 10:34:59 AM PDT 24 |
| Finished | Jul 01 10:35:06 AM PDT 24 |
| Peak memory | 205892 kb |
| Host | smart-0e69808e-9051-4a7b-8cd8-fabda59c22a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=3059647930 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.3059647930 |
| Directory | /workspace/8.usbdev_tl_intg_err/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.3294841128 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 184294895 ps |
| CPU time | 2.11 seconds |
| Started | Jul 01 10:35:02 AM PDT 24 |
| Finished | Jul 01 10:35:09 AM PDT 24 |
| Peak memory | 214124 kb |
| Host | smart-967b4df6-f19d-412a-848c-ca84fddb28a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294841128 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ =usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbde v_csr_mem_rw_with_rand_reset.3294841128 |
| Directory | /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1309858138 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 65115220 ps |
| CPU time | 0.93 seconds |
| Started | Jul 01 10:34:59 AM PDT 24 |
| Finished | Jul 01 10:35:03 AM PDT 24 |
| Peak memory | 205864 kb |
| Host | smart-774e2251-90f4-4aaf-a137-b79352dbe09f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc l +ntb_random_seed=1309858138 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1309858138 |
| Directory | /workspace/9.usbdev_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_intr_test.489478655 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 39558148 ps |
| CPU time | 0.66 seconds |
| Started | Jul 01 10:35:02 AM PDT 24 |
| Finished | Jul 01 10:35:07 AM PDT 24 |
| Peak memory | 205712 kb |
| Host | smart-2d5e9007-97b2-4731-8eee-9a152f97f581 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=489478655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.489478655 |
| Directory | /workspace/9.usbdev_intr_test/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.4192748798 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 201983133 ps |
| CPU time | 1.28 seconds |
| Started | Jul 01 10:35:01 AM PDT 24 |
| Finished | Jul 01 10:35:06 AM PDT 24 |
| Peak memory | 205876 kb |
| Host | smart-43573041-a0b5-41c7-a6cc-2b3e8bfeb0df |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/ hw/dv/tools/sim.tcl +ntb_random_seed=4192748798 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.4192748798 |
| Directory | /workspace/9.usbdev_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.4199888333 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 83023270 ps |
| CPU time | 2.27 seconds |
| Started | Jul 01 10:35:00 AM PDT 24 |
| Finished | Jul 01 10:35:06 AM PDT 24 |
| Peak memory | 222236 kb |
| Host | smart-48a69e70-a868-44e5-9ced-cdfc76fcd9e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=4199888333 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.4199888333 |
| Directory | /workspace/9.usbdev_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.542287943 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 1333377852 ps |
| CPU time | 4.68 seconds |
| Started | Jul 01 10:35:00 AM PDT 24 |
| Finished | Jul 01 10:35:08 AM PDT 24 |
| Peak memory | 205924 kb |
| Host | smart-6d9b7a4b-d68a-4a7d-82f1-9d3e37b5b5fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too ls/sim.tcl +ntb_random_seed=542287943 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.542287943 |
| Directory | /workspace/9.usbdev_tl_intg_err/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |