Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}
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Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY   EXPECTED   UNCOVERED   COVERED   PERCENT   
Variables 22 0 22 100.00
Crosses 72 0 72 100.00


Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
cp_intr_pin 18 0 18 100.00 100 1 1 0
cp_intr_pin_value 4 0 4 100.00 100 1 1 0


Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cp_intr_pins_all_values 72 0 72 100.00 100 1 1 0


Summary for Variable cp_intr_pin

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 18 0 18 100.00


User Defined Bins for cp_intr_pin

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_pins[0] 392 1 T1 2 T3 2 T7 2
all_pins[1] 392 1 T1 2 T3 2 T7 2
all_pins[2] 392 1 T1 2 T3 2 T7 2
all_pins[3] 392 1 T1 2 T3 2 T7 2
all_pins[4] 392 1 T1 2 T3 2 T7 2
all_pins[5] 392 1 T1 2 T3 2 T7 2
all_pins[6] 392 1 T1 2 T3 2 T7 2
all_pins[7] 392 1 T1 2 T3 2 T7 2
all_pins[8] 392 1 T1 2 T3 2 T7 2
all_pins[9] 392 1 T1 2 T3 2 T7 2
all_pins[10] 392 1 T1 2 T3 2 T7 2
all_pins[11] 392 1 T1 2 T3 2 T7 2
all_pins[12] 392 1 T1 2 T3 2 T7 2
all_pins[13] 392 1 T1 2 T3 2 T7 2
all_pins[14] 392 1 T1 2 T3 2 T7 2
all_pins[15] 392 1 T1 2 T3 2 T7 2
all_pins[16] 392 1 T1 2 T3 2 T7 2
all_pins[17] 392 1 T1 2 T3 2 T7 2


Summary for Variable cp_intr_pin_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr_pin_value

Bins
NAME   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
values[0x0] 5802 1 T1 36 T3 36 T7 36
values[0x1] 1254 1 T13 29 T14 28 T15 20
transitions[0x0=>0x1] 908 1 T13 21 T14 27 T15 9
transitions[0x1=>0x0] 923 1 T13 21 T14 27 T15 10


Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 72 0 72 100.00


Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins
cp_intr_pin   cp_intr_pin_value   COUNT   AT LEAST   TEST   COUNT   TEST   COUNT   TEST   COUNT   
all_pins[0] values[0x0] 326 1 T1 2 T3 2 T7 2
all_pins[0] values[0x1] 66 1 T13 3 T14 4 T15 1
all_pins[0] transitions[0x0=>0x1] 48 1 T13 2 T14 4 T16 1
all_pins[0] transitions[0x1=>0x0] 44 1 T13 1 T14 1 T16 1
all_pins[1] values[0x0] 330 1 T1 2 T3 2 T7 2
all_pins[1] values[0x1] 62 1 T13 2 T14 1 T15 1
all_pins[1] transitions[0x0=>0x1] 39 1 T13 2 T14 1 T16 1
all_pins[1] transitions[0x1=>0x0] 51 1 T13 1 T14 1 T16 2
all_pins[2] values[0x0] 318 1 T1 2 T3 2 T7 2
all_pins[2] values[0x1] 74 1 T13 1 T14 1 T15 1
all_pins[2] transitions[0x0=>0x1] 49 1 T13 1 T15 1 T16 2
all_pins[2] transitions[0x1=>0x0] 65 1 T13 2 T14 1 T16 1
all_pins[3] values[0x0] 302 1 T1 2 T3 2 T7 2
all_pins[3] values[0x1] 90 1 T13 2 T14 2 T16 1
all_pins[3] transitions[0x0=>0x1] 70 1 T13 2 T14 2 T16 1
all_pins[3] transitions[0x1=>0x0] 45 1 T14 1 T15 1 T16 2
all_pins[4] values[0x0] 327 1 T1 2 T3 2 T7 2
all_pins[4] values[0x1] 65 1 T14 1 T15 1 T16 2
all_pins[4] transitions[0x0=>0x1] 50 1 T14 1 T16 2 T19 2
all_pins[4] transitions[0x1=>0x0] 54 1 T13 2 T14 1 T19 1
all_pins[5] values[0x0] 323 1 T1 2 T3 2 T7 2
all_pins[5] values[0x1] 69 1 T13 2 T14 1 T15 1
all_pins[5] transitions[0x0=>0x1] 50 1 T13 2 T14 1 T15 1
all_pins[5] transitions[0x1=>0x0] 47 1 T16 2 T63 1 T67 3
all_pins[6] values[0x0] 326 1 T1 2 T3 2 T7 2
all_pins[6] values[0x1] 66 1 T16 2 T19 1 T17 3
all_pins[6] transitions[0x0=>0x1] 53 1 T16 1 T19 1 T17 2
all_pins[6] transitions[0x1=>0x0] 52 1 T13 3 T14 2 T16 4
all_pins[7] values[0x0] 327 1 T1 2 T3 2 T7 2
all_pins[7] values[0x1] 65 1 T13 3 T14 2 T16 5
all_pins[7] transitions[0x0=>0x1] 45 1 T13 1 T14 2 T16 5
all_pins[7] transitions[0x1=>0x0] 42 1 T13 1 T14 1 T15 2
all_pins[8] values[0x0] 330 1 T1 2 T3 2 T7 2
all_pins[8] values[0x1] 62 1 T13 3 T14 1 T15 2
all_pins[8] transitions[0x0=>0x1] 44 1 T13 3 T14 1 T19 1
all_pins[8] transitions[0x1=>0x0] 63 1 T13 1 T14 5 T16 2
all_pins[9] values[0x0] 311 1 T1 2 T3 2 T7 2
all_pins[9] values[0x1] 81 1 T13 1 T14 5 T15 2
all_pins[9] transitions[0x0=>0x1] 62 1 T14 5 T15 1 T16 1
all_pins[9] transitions[0x1=>0x0] 50 1 T13 1 T14 1 T16 2
all_pins[10] values[0x0] 323 1 T1 2 T3 2 T7 2
all_pins[10] values[0x1] 69 1 T13 2 T14 1 T15 1
all_pins[10] transitions[0x0=>0x1] 51 1 T13 2 T14 1 T15 1
all_pins[10] transitions[0x1=>0x0] 49 1 T13 2 T14 1 T15 1
all_pins[11] values[0x0] 325 1 T1 2 T3 2 T7 2
all_pins[11] values[0x1] 67 1 T13 2 T14 1 T15 1
all_pins[11] transitions[0x0=>0x1] 45 1 T14 1 T15 1 T19 1
all_pins[11] transitions[0x1=>0x0] 57 1 T14 3 T15 1 T16 3
all_pins[12] values[0x0] 313 1 T1 2 T3 2 T7 2
all_pins[12] values[0x1] 79 1 T13 2 T14 3 T15 1
all_pins[12] transitions[0x0=>0x1] 62 1 T13 2 T14 3 T15 1
all_pins[12] transitions[0x1=>0x0] 47 1 T17 4 T18 3 T63 1
all_pins[13] values[0x0] 328 1 T1 2 T3 2 T7 2
all_pins[13] values[0x1] 64 1 T16 2 T17 4 T18 4
all_pins[13] transitions[0x0=>0x1] 48 1 T16 2 T17 3 T18 2
all_pins[13] transitions[0x1=>0x0] 42 1 T14 2 T19 1 T37 2
all_pins[14] values[0x0] 334 1 T1 2 T3 2 T7 2
all_pins[14] values[0x1] 58 1 T14 2 T19 1 T37 2
all_pins[14] transitions[0x0=>0x1] 43 1 T14 2 T19 1 T37 2
all_pins[14] transitions[0x1=>0x0] 51 1 T14 1 T15 2 T16 1
all_pins[15] values[0x0] 326 1 T1 2 T3 2 T7 2
all_pins[15] values[0x1] 66 1 T14 1 T15 2 T16 1
all_pins[15] transitions[0x0=>0x1] 42 1 T14 1 T15 1 T17 2
all_pins[15] transitions[0x1=>0x0] 61 1 T13 4 T14 2 T15 2
all_pins[16] values[0x0] 307 1 T1 2 T3 2 T7 2
all_pins[16] values[0x1] 85 1 T13 4 T14 2 T15 3
all_pins[16] transitions[0x0=>0x1] 70 1 T13 3 T14 2 T15 1
all_pins[16] transitions[0x1=>0x0] 51 1 T13 1 T15 1 T17 2
all_pins[17] values[0x0] 326 1 T1 2 T3 2 T7 2
all_pins[17] values[0x1] 66 1 T13 2 T15 3 T16 1
all_pins[17] transitions[0x0=>0x1] 37 1 T13 1 T15 1 T16 1
all_pins[17] transitions[0x1=>0x0] 52 1 T13 2 T14 4 T16 1