Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	0	108	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	0	108	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	302	1		T13	7		T14	7		T15	4
all_values[1]	302	1		T13	7		T14	7		T15	4
all_values[2]	302	1		T13	7		T14	7		T15	4
all_values[3]	302	1		T13	7		T14	7		T15	4
all_values[4]	302	1		T13	7		T14	7		T15	4
all_values[5]	302	1		T13	7		T14	7		T15	4
all_values[6]	302	1		T13	7		T14	7		T15	4
all_values[7]	302	1		T13	7		T14	7		T15	4
all_values[8]	302	1		T13	7		T14	7		T15	4
all_values[9]	302	1		T13	7		T14	7		T15	4
all_values[10]	302	1		T13	7		T14	7		T15	4
all_values[11]	302	1		T13	7		T14	7		T15	4
all_values[12]	302	1		T13	7		T14	7		T15	4
all_values[13]	302	1		T13	7		T14	7		T15	4
all_values[14]	302	1		T13	7		T14	7		T15	4
all_values[15]	302	1		T13	7		T14	7		T15	4
all_values[16]	302	1		T13	7		T14	7		T15	4
all_values[17]	302	1		T13	7		T14	7		T15	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	2989	1		T13	72		T14	66		T15	46
auto[1]	2447	1		T13	54		T14	60		T15	26

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	847	1		T13	28		T14	12		T15	7
auto[1]	4589	1		T13	98		T14	114		T15	65

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	3127	1		T13	73		T14	69		T15	37
auto[1]	2309	1		T13	53		T14	57		T15	35

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	0	108	100.00
Automatically Generated Cross Bins	108	0	108	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	25	1		T19	3		T37	1		T17	1
all_values[0]	auto[0]	auto[0]	auto[1]	56	1		T14	1		T15	2		T16	2
all_values[0]	auto[0]	auto[1]	auto[0]	21	1		T37	1		T18	2		T63	1
all_values[0]	auto[0]	auto[1]	auto[1]	73	1		T13	4		T14	2		T16	2
all_values[0]	auto[1]	auto[0]	auto[1]	76	1		T13	2		T15	1		T16	3
all_values[0]	auto[1]	auto[1]	auto[1]	51	1		T13	1		T14	4		T15	1
all_values[1]	auto[0]	auto[0]	auto[0]	38	1		T13	2		T16	1		T37	1
all_values[1]	auto[0]	auto[0]	auto[1]	79	1		T13	2		T14	4		T15	1
all_values[1]	auto[0]	auto[1]	auto[0]	12	1		T65	1		T71	1		T72	4
all_values[1]	auto[0]	auto[1]	auto[1]	49	1		T14	1		T16	2		T19	2
all_values[1]	auto[1]	auto[0]	auto[1]	65	1		T13	1		T14	1		T15	2
all_values[1]	auto[1]	auto[1]	auto[1]	59	1		T13	2		T14	1		T15	1
all_values[2]	auto[0]	auto[0]	auto[0]	20	1		T16	1		T70	1		T73	1
all_values[2]	auto[0]	auto[0]	auto[1]	80	1		T13	3		T14	1		T16	3
all_values[2]	auto[0]	auto[1]	auto[0]	11	1		T17	1		T66	2		T71	1
all_values[2]	auto[0]	auto[1]	auto[1]	61	1		T13	1		T14	1		T15	3
all_values[2]	auto[1]	auto[0]	auto[1]	73	1		T13	3		T14	4		T15	1
all_values[2]	auto[1]	auto[1]	auto[1]	57	1		T14	1		T16	3		T19	2
all_values[3]	auto[0]	auto[0]	auto[0]	35	1		T15	3		T19	1		T63	2
all_values[3]	auto[0]	auto[0]	auto[1]	62	1		T13	2		T14	2		T16	3
all_values[3]	auto[0]	auto[1]	auto[0]	10	1		T15	1		T66	1		T74	1
all_values[3]	auto[0]	auto[1]	auto[1]	67	1		T13	1		T19	3		T17	5
all_values[3]	auto[1]	auto[0]	auto[1]	70	1		T13	2		T14	2		T16	3
all_values[3]	auto[1]	auto[1]	auto[1]	58	1		T13	2		T14	3		T16	1
all_values[4]	auto[0]	auto[0]	auto[0]	35	1		T14	2		T19	2		T66	1
all_values[4]	auto[0]	auto[0]	auto[1]	63	1		T13	4		T14	1		T15	2
all_values[4]	auto[0]	auto[1]	auto[0]	21	1		T18	3		T63	2		T66	1
all_values[4]	auto[0]	auto[1]	auto[1]	50	1		T14	1		T15	1		T19	1
all_values[4]	auto[1]	auto[0]	auto[1]	86	1		T13	2		T14	3		T15	1
all_values[4]	auto[1]	auto[1]	auto[1]	47	1		T13	1		T16	1		T19	1
all_values[5]	auto[0]	auto[0]	auto[0]	33	1		T13	1		T14	1		T16	2
all_values[5]	auto[0]	auto[0]	auto[1]	67	1		T13	3		T14	1		T15	2
all_values[5]	auto[0]	auto[1]	auto[0]	20	1		T67	3		T68	1		T74	1
all_values[5]	auto[0]	auto[1]	auto[1]	63	1		T14	3		T15	1		T16	1
all_values[5]	auto[1]	auto[0]	auto[1]	55	1		T13	2		T14	1		T15	1
all_values[5]	auto[1]	auto[1]	auto[1]	64	1		T13	1		T14	1		T16	1
all_values[6]	auto[0]	auto[0]	auto[0]	31	1		T13	1		T14	1		T15	1
all_values[6]	auto[0]	auto[0]	auto[1]	61	1		T14	1		T15	1		T16	1
all_values[6]	auto[0]	auto[1]	auto[0]	21	1		T14	2		T19	1		T37	1
all_values[6]	auto[0]	auto[1]	auto[1]	61	1		T13	4		T14	1		T16	1
all_values[6]	auto[1]	auto[0]	auto[1]	66	1		T13	1		T14	2		T15	1
all_values[6]	auto[1]	auto[1]	auto[1]	62	1		T13	1		T15	1		T16	4
all_values[7]	auto[0]	auto[0]	auto[0]	29	1		T19	1		T70	1		T63	1
all_values[7]	auto[0]	auto[0]	auto[1]	72	1		T13	2		T14	2		T15	2
all_values[7]	auto[0]	auto[1]	auto[0]	15	1		T17	1		T68	4		T75	1
all_values[7]	auto[0]	auto[1]	auto[1]	60	1		T13	2		T14	3		T16	1
all_values[7]	auto[1]	auto[0]	auto[1]	71	1		T13	1		T15	1		T16	2
all_values[7]	auto[1]	auto[1]	auto[1]	55	1		T13	2		T14	2		T15	1
all_values[8]	auto[0]	auto[0]	auto[0]	33	1		T16	2		T19	3		T17	3
all_values[8]	auto[0]	auto[0]	auto[1]	68	1		T13	1		T14	2		T15	1
all_values[8]	auto[0]	auto[1]	auto[0]	19	1		T19	1		T17	2		T66	1
all_values[8]	auto[0]	auto[1]	auto[1]	59	1		T13	1		T14	1		T16	2
all_values[8]	auto[1]	auto[0]	auto[1]	69	1		T13	3		T14	3		T15	1
all_values[8]	auto[1]	auto[1]	auto[1]	54	1		T13	2		T14	1		T15	2
all_values[9]	auto[0]	auto[0]	auto[0]	38	1		T13	1		T16	1		T19	4
all_values[9]	auto[0]	auto[0]	auto[1]	56	1		T13	1		T16	4		T17	3
all_values[9]	auto[0]	auto[1]	auto[0]	17	1		T19	1		T70	4		T67	2
all_values[9]	auto[0]	auto[1]	auto[1]	59	1		T14	3		T15	2		T19	1
all_values[9]	auto[1]	auto[0]	auto[1]	65	1		T13	4		T14	1		T15	1
all_values[9]	auto[1]	auto[1]	auto[1]	67	1		T13	1		T14	3		T15	1
all_values[10]	auto[0]	auto[0]	auto[0]	31	1		T13	1		T14	2		T15	1
all_values[10]	auto[0]	auto[0]	auto[1]	69	1		T13	2		T14	1		T15	1
all_values[10]	auto[0]	auto[1]	auto[0]	15	1		T13	1		T14	1		T16	1
all_values[10]	auto[0]	auto[1]	auto[1]	58	1		T13	2		T14	1		T16	1
all_values[10]	auto[1]	auto[0]	auto[1]	78	1		T14	1		T15	1		T19	1
all_values[10]	auto[1]	auto[1]	auto[1]	51	1		T13	1		T14	1		T15	1
all_values[11]	auto[0]	auto[0]	auto[0]	40	1		T13	1		T16	1		T17	1
all_values[11]	auto[0]	auto[0]	auto[1]	57	1		T14	4		T15	1		T16	1
all_values[11]	auto[0]	auto[1]	auto[0]	14	1		T13	2		T14	1		T67	1
all_values[11]	auto[0]	auto[1]	auto[1]	74	1		T13	1		T15	1		T16	3
all_values[11]	auto[1]	auto[0]	auto[1]	64	1		T14	1		T15	2		T16	2
all_values[11]	auto[1]	auto[1]	auto[1]	53	1		T13	3		T14	1		T19	2
all_values[12]	auto[0]	auto[0]	auto[0]	31	1		T13	1		T16	1		T37	1
all_values[12]	auto[0]	auto[0]	auto[1]	61	1		T13	1		T14	1		T15	1
all_values[12]	auto[0]	auto[1]	auto[0]	14	1		T37	1		T70	1		T63	2
all_values[12]	auto[0]	auto[1]	auto[1]	62	1		T13	1		T14	1		T16	2
all_values[12]	auto[1]	auto[0]	auto[1]	63	1		T13	2		T14	2		T15	2
all_values[12]	auto[1]	auto[1]	auto[1]	71	1		T13	2		T14	3		T15	1
all_values[13]	auto[0]	auto[0]	auto[0]	31	1		T13	2		T14	1		T16	1
all_values[13]	auto[0]	auto[0]	auto[1]	67	1		T14	1		T15	2		T16	1
all_values[13]	auto[0]	auto[1]	auto[0]	19	1		T13	5		T70	2		T63	1
all_values[13]	auto[0]	auto[1]	auto[1]	53	1		T14	1		T16	1		T19	1
all_values[13]	auto[1]	auto[0]	auto[1]	74	1		T14	4		T15	2		T16	2
all_values[13]	auto[1]	auto[1]	auto[1]	58	1		T16	2		T17	3		T18	4
all_values[14]	auto[0]	auto[0]	auto[0]	23	1		T13	4		T16	1		T66	1
all_values[14]	auto[0]	auto[0]	auto[1]	69	1		T13	1		T14	1		T15	2
all_values[14]	auto[0]	auto[1]	auto[0]	22	1		T16	1		T70	1		T63	2
all_values[14]	auto[0]	auto[1]	auto[1]	65	1		T14	4		T16	1		T19	1
all_values[14]	auto[1]	auto[0]	auto[1]	80	1		T13	2		T14	1		T15	2
all_values[14]	auto[1]	auto[1]	auto[1]	43	1		T14	1		T19	1		T37	1
all_values[15]	auto[0]	auto[0]	auto[0]	29	1		T13	2		T19	1		T67	2
all_values[15]	auto[0]	auto[0]	auto[1]	60	1		T13	1		T14	2		T15	1
all_values[15]	auto[0]	auto[1]	auto[0]	16	1		T13	1		T17	1		T18	1
all_values[15]	auto[0]	auto[1]	auto[1]	68	1		T14	2		T15	1		T16	1
all_values[15]	auto[1]	auto[0]	auto[1]	72	1		T13	3		T14	2		T15	1
all_values[15]	auto[1]	auto[1]	auto[1]	57	1		T14	1		T15	1		T16	3
all_values[16]	auto[0]	auto[0]	auto[0]	17	1		T15	1		T37	1		T17	1
all_values[16]	auto[0]	auto[0]	auto[1]	46	1		T13	1		T14	1		T16	1
all_values[16]	auto[0]	auto[1]	auto[0]	9	1		T70	1		T76	1		T77	1
all_values[16]	auto[0]	auto[1]	auto[1]	80	1		T13	3		T14	3		T15	1
all_values[16]	auto[1]	auto[0]	auto[1]	80	1		T13	2		T16	2		T19	1
all_values[16]	auto[1]	auto[1]	auto[1]	70	1		T13	1		T14	3		T15	2
all_values[17]	auto[0]	auto[0]	auto[0]	38	1		T13	1		T16	1		T19	1
all_values[17]	auto[0]	auto[0]	auto[1]	60	1		T14	2		T16	2		T19	3
all_values[17]	auto[0]	auto[1]	auto[0]	14	1		T13	2		T14	1		T19	1
all_values[17]	auto[0]	auto[1]	auto[1]	65	1		T13	1		T14	1		T15	1
all_values[17]	auto[1]	auto[0]	auto[1]	72	1		T13	1		T14	3		T15	1
all_values[17]	auto[1]	auto[1]	auto[1]	53	1		T13	2		T15	2		T19	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal