Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60739	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	61374	1		T1	27		T2	1481		T3	24

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	75666	1		T1	20		T2	1387		T3	20
values[0x0]	23004	1		T1	7		T2	683		T3	7
values[0x1]	23443	1		T1	13		T2	702		T3	13

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42214	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	79899	1		T1	32		T2	1793		T3	32

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	496	1		T7	3		T9	11		T8	1
valid_sources[0x01]	417	1		T9	11		T8	5		T6	8
valid_sources[0x02]	477	1		T4	3		T9	6		T8	2
valid_sources[0x03]	479	1		T4	19		T9	7		T6	17
valid_sources[0x04]	456	1		T9	10		T8	1		T6	17
valid_sources[0x05]	404	1		T7	2		T4	3		T9	4
valid_sources[0x06]	518	1		T7	1		T4	2		T9	9
valid_sources[0x07]	345	1		T9	6		T8	3		T6	9
valid_sources[0x08]	676	1		T3	2		T4	5		T9	11
valid_sources[0x09]	565	1		T7	5		T4	1		T9	7
valid_sources[0x0a]	371	1		T9	8		T6	15		T24	4
valid_sources[0x0b]	405	1		T9	8		T8	4		T6	9
valid_sources[0x0c]	402	1		T9	7		T8	8		T6	9
valid_sources[0x0d]	501	1		T7	4		T9	2		T6	12
valid_sources[0x0e]	392	1		T9	4		T8	1		T6	6
valid_sources[0x0f]	590	1		T2	112		T7	5		T4	7
valid_sources[0x10]	405	1		T7	2		T9	6		T8	2
valid_sources[0x11]	696	1		T7	4		T9	6		T8	4
valid_sources[0x12]	375	1		T3	1		T7	6		T9	6
valid_sources[0x13]	455	1		T9	5		T8	2		T6	5
valid_sources[0x14]	581	1		T2	127		T7	1		T4	10
valid_sources[0x15]	475	1		T9	5		T8	1		T6	9
valid_sources[0x16]	523	1		T9	3		T8	1		T6	13
valid_sources[0x17]	577	1		T2	128		T7	1		T9	4
valid_sources[0x18]	505	1		T2	128		T7	4		T4	2
valid_sources[0x19]	385	1		T7	8		T9	11		T6	4
valid_sources[0x1a]	954	1		T7	2		T9	4		T8	3
valid_sources[0x1b]	475	1		T9	5		T8	1		T6	9
valid_sources[0x1c]	390	1		T9	6		T8	3		T6	6
valid_sources[0x1d]	398	1		T7	3		T9	9		T8	1
valid_sources[0x1e]	543	1		T2	128		T9	9		T8	3
valid_sources[0x1f]	392	1		T4	8		T9	9		T8	3
valid_sources[0x20]	450	1		T9	7		T8	3		T6	11
valid_sources[0x21]	426	1		T4	2		T9	6		T8	2
valid_sources[0x22]	433	1		T7	4		T9	8		T8	1
valid_sources[0x23]	502	1		T2	128		T7	7		T9	9
valid_sources[0x24]	439	1		T7	1		T9	10		T8	5
valid_sources[0x25]	422	1		T4	1		T9	6		T8	3
valid_sources[0x26]	444	1		T7	2		T9	13		T8	1
valid_sources[0x27]	673	1		T9	4		T8	2		T16	4
valid_sources[0x28]	468	1		T9	10		T8	2		T6	15
valid_sources[0x29]	389	1		T4	4		T9	4		T8	4
valid_sources[0x2a]	610	1		T2	136		T7	9		T5	2
valid_sources[0x2b]	448	1		T7	1		T9	7		T8	1
valid_sources[0x2c]	555	1		T2	128		T7	2		T4	1
valid_sources[0x2d]	638	1		T2	128		T7	2		T4	4
valid_sources[0x2e]	425	1		T7	2		T9	8		T6	15
valid_sources[0x2f]	447	1		T7	6		T9	5		T8	2
valid_sources[0x30]	362	1		T4	4		T9	4		T8	1
valid_sources[0x31]	365	1		T4	8		T9	7		T6	8
valid_sources[0x32]	391	1		T3	5		T9	5		T8	1
valid_sources[0x33]	577	1		T7	2		T9	6		T8	3
valid_sources[0x34]	334	1		T7	6		T4	2		T9	8
valid_sources[0x35]	503	1		T2	131		T4	14		T9	7
valid_sources[0x36]	370	1		T9	11		T8	2		T6	8
valid_sources[0x37]	716	1		T9	4		T6	11		T24	1
valid_sources[0x38]	548	1		T7	7		T9	12		T8	3
valid_sources[0x39]	484	1		T7	1		T9	3		T8	1
valid_sources[0x3a]	399	1		T3	1		T7	3		T4	10
valid_sources[0x3b]	336	1		T9	7		T8	2		T6	4
valid_sources[0x3c]	459	1		T7	1		T9	10		T8	1
valid_sources[0x3d]	438	1		T7	1		T4	2		T9	9
valid_sources[0x3e]	435	1		T7	1		T5	7		T9	4
valid_sources[0x3f]	450	1		T9	11		T8	1		T6	9
valid_sources[0x40]	438	1		T9	10		T8	2		T6	16
valid_sources[0x41]	626	1		T5	6		T9	14		T8	1
valid_sources[0x42]	527	1		T9	5		T8	3		T6	26
valid_sources[0x43]	417	1		T9	3		T8	1		T6	8
valid_sources[0x44]	628	1		T7	1		T9	8		T8	1
valid_sources[0x45]	432	1		T9	8		T8	5		T6	8
valid_sources[0x46]	472	1		T9	6		T8	1		T16	1
valid_sources[0x47]	494	1		T7	3		T9	12		T8	2
valid_sources[0x48]	443	1		T7	4		T4	4		T9	3
valid_sources[0x49]	492	1		T9	4		T8	3		T6	6
valid_sources[0x4a]	508	1		T9	6		T8	2		T6	4
valid_sources[0x4b]	372	1		T9	6		T8	4		T6	6
valid_sources[0x4c]	429	1		T3	1		T7	1		T9	8
valid_sources[0x4d]	354	1		T4	5		T9	8		T8	1
valid_sources[0x4e]	415	1		T4	6		T9	3		T8	1
valid_sources[0x4f]	454	1		T9	7		T8	2		T6	14
valid_sources[0x50]	474	1		T7	1		T5	3		T9	6
valid_sources[0x51]	424	1		T7	13		T9	3		T8	5
valid_sources[0x52]	644	1		T9	8		T8	1		T6	4
valid_sources[0x53]	373	1		T9	12		T8	3		T6	4
valid_sources[0x54]	372	1		T4	3		T9	7		T8	4
valid_sources[0x55]	558	1		T7	1		T4	1		T9	6
valid_sources[0x56]	337	1		T7	3		T9	2		T8	2
valid_sources[0x57]	639	1		T7	1		T4	3		T9	11
valid_sources[0x58]	682	1		T7	3		T9	6		T8	3
valid_sources[0x59]	444	1		T4	5		T9	8		T6	12
valid_sources[0x5a]	421	1		T7	2		T9	6		T8	3
valid_sources[0x5b]	369	1		T9	9		T8	2		T6	1
valid_sources[0x5c]	468	1		T4	25		T9	10		T8	3
valid_sources[0x5d]	530	1		T4	14		T9	10		T8	3
valid_sources[0x5e]	442	1		T7	1		T9	6		T6	7
valid_sources[0x5f]	414	1		T9	7		T8	1		T6	9
valid_sources[0x60]	808	1		T9	6		T8	5		T6	5
valid_sources[0x61]	543	1		T7	4		T4	15		T9	5
valid_sources[0x62]	407	1		T7	1		T4	4		T9	4
valid_sources[0x63]	453	1		T3	1		T4	16		T9	5
valid_sources[0x64]	451	1		T7	3		T9	7		T8	2
valid_sources[0x65]	401	1		T3	3		T4	12		T9	5
valid_sources[0x66]	467	1		T9	9		T8	3		T6	8
valid_sources[0x67]	378	1		T9	6		T8	2		T16	1
valid_sources[0x68]	695	1		T9	4		T8	1		T24	3
valid_sources[0x69]	471	1		T3	1		T4	4		T9	12
valid_sources[0x6a]	527	1		T2	124		T9	8		T8	3
valid_sources[0x6b]	669	1		T3	1		T7	1		T4	1
valid_sources[0x6c]	582	1		T1	40		T3	3		T7	3
valid_sources[0x6d]	468	1		T7	4		T9	10		T8	3
valid_sources[0x6e]	417	1		T7	2		T9	7		T8	1
valid_sources[0x6f]	349	1		T9	6		T8	1		T16	1
valid_sources[0x70]	451	1		T7	3		T4	13		T9	10
valid_sources[0x71]	464	1		T9	8		T8	1		T6	13
valid_sources[0x72]	443	1		T7	2		T4	2		T5	2
valid_sources[0x73]	370	1		T9	6		T8	1		T6	12
valid_sources[0x74]	468	1		T9	8		T8	3		T6	9
valid_sources[0x75]	579	1		T7	1		T4	8		T9	4
valid_sources[0x76]	367	1		T4	2		T9	4		T8	4
valid_sources[0x77]	456	1		T7	18		T4	4		T9	6
valid_sources[0x78]	558	1		T2	128		T9	7		T8	2
valid_sources[0x79]	453	1		T3	2		T7	1		T9	9
valid_sources[0x7a]	393	1		T9	3		T8	3		T6	3
valid_sources[0x7b]	437	1		T3	1		T9	9		T8	2
valid_sources[0x7c]	449	1		T7	1		T9	6		T8	1
valid_sources[0x7d]	442	1		T7	1		T9	1		T8	3
valid_sources[0x7e]	406	1		T4	1		T9	11		T8	2
valid_sources[0x7f]	406	1		T4	9		T9	7		T8	2
valid_sources[0x80]	404	1		T7	7		T9	12		T8	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

25174

1

T1

12

T2

715

T3

11

values[0x0]

all_enables

biggest_size

19469

1

T1

7

T2

453

T3

7

values[0x1]

all_enables

biggest_size

16731

1

T1

8

T2

313

T3

6