Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	75939	1		T1	13		T2	1291		T3	16
full_word	62464	1		T1	27		T2	1481		T3	24

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	138103	1		T1	40		T2	2772		T3	40
auto[TlIntgErrCmd]	107	1		T6	8		T26	3		T44	3
auto[TlIntgErrData]	95	1		T6	4		T26	2		T44	10
auto[TlIntgErrBoth]	98	1		T6	8		T26	5		T44	7

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	77719	1		T1	20		T2	1387		T3	20
auto[1]	60684	1		T1	20		T2	1385		T3	20

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	52198	1		T1	8		T2	672		T3	9
auto[TlIntgErrNone]	partial	auto[1]	23469	1		T1	5		T2	619		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	25389	1		T1	12		T2	715		T3	11
auto[TlIntgErrNone]	full_word	auto[1]	37047	1		T1	15		T2	766		T3	13
auto[TlIntgErrCmd]	partial	auto[0]	45	1		T6	3		T26	1		T44	1
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T6	3		T26	1		T44	2
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T26	1		T68	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	7	1		T6	2		T68	1		T69	1
auto[TlIntgErrData]	partial	auto[0]	46	1		T6	1		T26	1		T44	5
auto[TlIntgErrData]	partial	auto[1]	40	1		T6	2		T26	1		T44	4
auto[TlIntgErrData]	full_word	auto[0]	5	1		T70	1		T71	1		T69	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T6	1		T44	1		T68	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1		T6	1		T26	3		T44	1
auto[TlIntgErrBoth]	partial	auto[1]	57	1		T6	6		T26	1		T44	6
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T6	1		T50	1		T43	1
auto[TlIntgErrBoth]	full_word	auto[1]	7	1		T26	1		T50	1		T71	1