Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
22.84	0.00	0.00	91.36		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1925673	12577	0	0
ep_in_enable_rd_A	1925673	4693	0	0
ep_out_enable_rd_A	1925673	4641	0	0
in_iso_rd_A	1925673	4779	0	0
intr_enable_rd_A	1925673	6032	0	0
out_iso_rd_A	1925673	5063	0	0
phy_config_rd_A	1925673	3101	0	0
phy_pins_drive_rd_A	1925673	4190	0	0
rxenable_setup_rd_A	1925673	5111	0	0
set_nak_out_rd_A	1925673	4629	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925673	12577	0	0
T4	4861	12	0	0
T5	3847	0	0	0
T6	39855	6	0	0
T7	15030	790	0	0
T8	5784	859	0	0
T9	6004	0	0	0
T16	1978	0	0	0
T17	9044	379	0	0
T18	0	967	0	0
T19	0	36	0	0
T20	0	928	0	0
T21	0	7	0	0
T24	10189	0	0	0
T25	5636	0	0	0
T26	0	3	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925673	4693	0	0
T14	2025	0	0	0
T15	4112	0	0	0
T17	9044	0	0	0
T18	5647	0	0	0
T19	5652	0	0	0
T24	10189	58	0	0
T25	5636	4	0	0
T27	0	22	0	0
T37	70511	0	0	0
T38	2584	0	0	0
T39	89873	481	0	0
T49	0	20	0	0
T50	0	479	0	0
T51	0	103	0	0
T52	0	44	0	0
T53	0	99	0	0
T54	0	14	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925673	4641	0	0
T14	2025	0	0	0
T15	4112	0	0	0
T17	9044	0	0	0
T18	5647	0	0	0
T19	5652	0	0	0
T21	0	2	0	0
T24	10189	21	0	0
T25	5636	4	0	0
T27	0	5	0	0
T37	70511	0	0	0
T38	2584	0	0	0
T39	89873	405	0	0
T45	0	7	0	0
T49	0	55	0	0
T50	0	420	0	0
T51	0	23	0	0
T52	0	38	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925673	4779	0	0
T14	2025	0	0	0
T15	4112	0	0	0
T17	9044	0	0	0
T18	5647	0	0	0
T19	5652	0	0	0
T21	0	31	0	0
T24	10189	28	0	0
T25	5636	59	0	0
T27	0	15	0	0
T37	70511	0	0	0
T38	2584	0	0	0
T39	89873	409	0	0
T49	0	59	0	0
T50	0	498	0	0
T51	0	24	0	0
T52	0	12	0	0
T53	0	20	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925673	6032	0	0
T6	39855	0	0	0
T14	2025	0	0	0
T15	4112	13	0	0
T16	1978	8	0	0
T17	9044	0	0	0
T18	5647	0	0	0
T21	0	57	0	0
T24	10189	36	0	0
T25	5636	58	0	0
T27	0	34	0	0
T37	70511	0	0	0
T38	2584	0	0	0
T39	0	383	0	0
T49	0	73	0	0
T55	0	12	0	0
T56	0	16	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925673	5063	0	0
T14	2025	0	0	0
T15	4112	0	0	0
T17	9044	0	0	0
T18	5647	0	0	0
T19	5652	0	0	0
T24	10189	28	0	0
T25	5636	31	0	0
T27	0	2	0	0
T37	70511	0	0	0
T38	2584	0	0	0
T39	89873	445	0	0
T45	0	1	0	0
T49	0	51	0	0
T50	0	337	0	0
T51	0	63	0	0
T52	0	77	0	0
T53	0	66	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925673	3101	0	0
T4	4861	0	0	0
T5	3847	0	0	0
T6	39855	0	0	0
T7	15030	2	0	0
T8	5784	0	0	0
T9	6004	0	0	0
T16	1978	0	0	0
T17	9044	0	0	0
T21	0	10	0	0
T24	10189	86	0	0
T25	5636	28	0	0
T27	0	13	0	0
T39	0	401	0	0
T49	0	31	0	0
T50	0	199	0	0
T51	0	17	0	0
T52	0	28	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925673	4190	0	0
T10	0	5	0	0
T14	2025	0	0	0
T15	4112	0	0	0
T17	9044	0	0	0
T18	5647	0	0	0
T19	5652	0	0	0
T21	0	26	0	0
T24	10189	30	0	0
T25	5636	9	0	0
T27	0	23	0	0
T37	70511	0	0	0
T38	2584	0	0	0
T39	89873	450	0	0
T45	0	5	0	0
T49	0	25	0	0
T50	0	346	0	0
T51	0	62	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925673	5111	0	0
T10	0	5	0	0
T14	2025	0	0	0
T15	4112	0	0	0
T17	9044	0	0	0
T18	5647	0	0	0
T19	5652	0	0	0
T24	10189	44	0	0
T25	5636	6	0	0
T37	70511	0	0	0
T38	2584	0	0	0
T39	89873	479	0	0
T49	0	55	0	0
T50	0	516	0	0
T51	0	17	0	0
T52	0	40	0	0
T53	0	18	0	0
T54	0	7	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925673	4629	0	0
T10	0	3	0	0
T14	2025	0	0	0
T15	4112	0	0	0
T17	9044	0	0	0
T18	5647	0	0	0
T19	5652	0	0	0
T21	0	12	0	0
T24	10189	65	0	0
T25	5636	50	0	0
T27	0	5	0	0
T37	70511	0	0	0
T38	2584	0	0	0
T39	89873	496	0	0
T49	0	16	0	0
T50	0	455	0	0
T51	0	56	0	0
T52	0	44	0	0