Unified Coverage Report :: Module

Module : prim_sync_reqack

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
22.92	50.00	0.00			41.67	0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg.u_wake_events_cdc.u_arb.gen_wr_req.u_dst_update_sync	22.92	50.00	0.00			41.67	0.00

Module Instance : tb.dut.u_reg.u_wake_events_cdc.u_arb.gen_wr_req.u_dst_update_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
22.92	50.00	0.00			41.67	0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
31.88	62.50	0.00			65.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
23.43	38.00	20.93			34.78	0.00	u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_nrz_hs_protocol.ack_sync	100.00	100.00				100.00
gen_nrz_hs_protocol.req_sync	100.00	100.00				100.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_sync_reqack

	Line No.	Total	Covered	Percent
TOTAL		36	18	50.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	194	1	0	0.00
CONT_ASSIGN	195	1	1	100.00
ALWAYS	219	12	0	0.00
ALWAYS	263	12	7	58.33
ALWAYS	307	5	5	100.00
ALWAYS	316	5	5	100.00
CONT_ASSIGN	335	0	0
ALWAYS	339	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
194	0	1
195	1	1
219	0	1
222	0	1
223	0	1
225	0	1
229	0	1
230	0	1
233	0	1
234	0	1
			==> MISSING_ELSE
241	0	1
242	0	1
245	0	1
246	0	1
			==> MISSING_ELSE
263	1	1
266	1	1
267	1	1
269	1	1
273	1	1
274	1	1
277	1	1
278	0	1
			MISSING_ELSE
285	0	1
286	0	1
289	0	1
290	0	1
			==> MISSING_ELSE
307	1	1
308	1	1
309	1	1
311	1	1
312	1	1
316	1	1
317	1	1
318	1	1
320	1	1
321	1	1
335		unreachable
339		unreachable
340		unreachable
341		unreachable
342		unreachable
			==> MISSING_ELSE

Cond Coverage for Module : prim_sync_reqack

	Total	Percent
Conditions	6	0.00
Logical	6	0.00
Non-Logical	0
Event	0

 LINE       194
 EXPRESSION (src_req_i & src_ack_o)
             ----1----   ----2----

-1-	-2-	Status
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       195
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

Branch Coverage for Module : prim_sync_reqack

	Line No.	Total	Covered	Percent
Branches		12	5	41.67
CASE	225	4	0	0.00
CASE	269	4	1	25.00
IF	307	2	2	100.00
IF	316	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack.sv was not found/opened, so annotated branch coverage report could not be generated.



	LineNo.	Expression
-1-:	225	case (gen_nrz_hs_protocol.src_fsm_cs)
-2-:	233	if (gen_nrz_hs_protocol.src_handshake)
-3-:	245	if (gen_nrz_hs_protocol.src_handshake)

Branches:

-1-	-2-	-3-	Status
EVEN	1	-	Not Covered
EVEN	0	-	Not Covered
ODD	-	1	Not Covered
ODD	-	0	Not Covered



	LineNo.	Expression
-1-:	269	case (gen_nrz_hs_protocol.dst_fsm_cs)
-2-:	277	if (gen_nrz_hs_protocol.dst_handshake)
-3-:	289	if (gen_nrz_hs_protocol.dst_handshake)

Branches:

-1-	-2-	-3-	Status	Tests
EVEN	1	-	Not Covered
EVEN	0	-	Covered	T1,T2,T3
ODD	-	1	Not Covered
ODD	-	0	Not Covered



	LineNo.	Expression
-1-:	307	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



	LineNo.	Expression
-1-:	316	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Module : prim_sync_reqack

	Total	Attempted	Percent	Percent
Assertions	2	2	100.00	0.00
Cover properties	0	0
Cover sequences	0	0
Total	2	2	100.00	0.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
SyncReqAckAckNeedsReq	1925673	0	0	0
SyncReqAckHoldReq	21320	0	0	0

SyncReqAckAckNeedsReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	1925673	0	0	0

SyncReqAckHoldReq

Name	Attempts	Real Successes	Failures	Incomplete
Total	21320	0	0	0