Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60958	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	60513	1		T1	736		T2	24		T3	1485

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	75344	1		T1	456		T2	20		T3	1446
values[0x0]	22730	1		T1	135		T2	7		T3	743
values[0x1]	23397	1		T1	145		T2	13		T3	702

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42423	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	79048	1		T1	736		T2	30		T3	1784

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	446	1		T1	4		T3	7		T4	3
valid_sources[0x01]	495	1		T1	1		T3	29		T4	2
valid_sources[0x02]	478	1		T1	4		T3	8		T4	4
valid_sources[0x03]	406	1		T1	2		T3	13		T4	3
valid_sources[0x04]	399	1		T1	1		T3	15		T4	4
valid_sources[0x05]	476	1		T1	1		T3	18		T5	7
valid_sources[0x06]	351	1		T1	4		T3	12		T4	2
valid_sources[0x07]	409	1		T1	5		T3	10		T5	15
valid_sources[0x08]	390	1		T1	2		T3	17		T4	1
valid_sources[0x09]	509	1		T1	2		T3	14		T4	1
valid_sources[0x0a]	356	1		T1	1		T3	8		T4	3
valid_sources[0x0b]	443	1		T1	4		T3	26		T4	2
valid_sources[0x0c]	513	1		T1	1		T3	6		T4	7
valid_sources[0x0d]	725	1		T1	3		T3	5		T4	2
valid_sources[0x0e]	391	1		T1	1		T3	9		T4	3
valid_sources[0x0f]	466	1		T1	2		T3	18		T4	4
valid_sources[0x10]	423	1		T1	1		T3	2		T4	8
valid_sources[0x11]	439	1		T1	5		T2	2		T3	6
valid_sources[0x12]	355	1		T1	1		T3	7		T4	1
valid_sources[0x13]	496	1		T1	3		T3	11		T4	2
valid_sources[0x14]	713	1		T3	6		T4	3		T5	7
valid_sources[0x15]	388	1		T1	1		T3	6		T4	3
valid_sources[0x16]	374	1		T1	2		T2	2		T3	17
valid_sources[0x17]	555	1		T1	4		T3	13		T4	3
valid_sources[0x18]	275	1		T1	2		T3	9		T4	4
valid_sources[0x19]	447	1		T1	3		T3	11		T4	4
valid_sources[0x1a]	337	1		T1	3		T3	5		T4	2
valid_sources[0x1b]	433	1		T1	3		T3	13		T4	4
valid_sources[0x1c]	698	1		T1	1		T3	9		T4	4
valid_sources[0x1d]	397	1		T1	3		T3	4		T4	3
valid_sources[0x1e]	486	1		T1	4		T3	14		T4	4
valid_sources[0x1f]	425	1		T1	1		T3	10		T4	2
valid_sources[0x20]	478	1		T1	6		T3	7		T4	4
valid_sources[0x21]	441	1		T1	7		T2	2		T3	18
valid_sources[0x22]	384	1		T1	2		T2	1		T3	13
valid_sources[0x23]	400	1		T1	1		T3	21		T4	1
valid_sources[0x24]	510	1		T1	1		T3	15		T4	2
valid_sources[0x25]	398	1		T1	4		T3	12		T4	4
valid_sources[0x26]	433	1		T1	3		T3	10		T4	5
valid_sources[0x27]	484	1		T1	1		T3	4		T4	2
valid_sources[0x28]	331	1		T1	3		T3	7		T4	3
valid_sources[0x29]	460	1		T1	3		T3	5		T4	3
valid_sources[0x2a]	486	1		T1	3		T3	8		T4	1
valid_sources[0x2b]	545	1		T1	4		T3	8		T4	4
valid_sources[0x2c]	506	1		T1	1		T3	22		T5	19
valid_sources[0x2d]	475	1		T3	6		T4	5		T5	14
valid_sources[0x2e]	412	1		T1	2		T3	17		T4	6
valid_sources[0x2f]	355	1		T1	2		T2	1		T3	10
valid_sources[0x30]	297	1		T1	3		T3	8		T4	2
valid_sources[0x31]	765	1		T1	4		T3	10		T4	2
valid_sources[0x32]	491	1		T1	4		T3	6		T4	3
valid_sources[0x33]	405	1		T1	1		T2	1		T3	15
valid_sources[0x34]	496	1		T1	2		T3	3		T4	5
valid_sources[0x35]	369	1		T1	1		T3	16		T4	2
valid_sources[0x36]	680	1		T1	5		T3	12		T5	22
valid_sources[0x37]	343	1		T1	2		T3	3		T4	3
valid_sources[0x38]	957	1		T1	1		T3	13		T4	3
valid_sources[0x39]	338	1		T1	6		T3	9		T4	4
valid_sources[0x3a]	739	1		T1	4		T3	23		T4	1
valid_sources[0x3b]	426	1		T1	1		T2	1		T3	3
valid_sources[0x3c]	371	1		T3	18		T4	5		T5	4
valid_sources[0x3d]	512	1		T1	4		T3	6		T4	7
valid_sources[0x3e]	428	1		T1	2		T3	18		T4	2
valid_sources[0x3f]	453	1		T1	1		T3	2		T4	6
valid_sources[0x40]	428	1		T1	1		T3	16		T4	2
valid_sources[0x41]	410	1		T1	4		T2	2		T3	8
valid_sources[0x42]	479	1		T1	3		T3	20		T4	3
valid_sources[0x43]	653	1		T1	1		T3	14		T4	1
valid_sources[0x44]	481	1		T1	1		T3	7		T4	1
valid_sources[0x45]	677	1		T1	2		T3	3		T4	1
valid_sources[0x46]	371	1		T1	2		T3	10		T4	4
valid_sources[0x47]	485	1		T1	3		T3	13		T4	1
valid_sources[0x48]	554	1		T1	4		T3	8		T4	7
valid_sources[0x49]	372	1		T1	3		T3	3		T5	5
valid_sources[0x4a]	301	1		T3	10		T4	3		T5	6
valid_sources[0x4b]	427	1		T1	6		T3	19		T4	5
valid_sources[0x4c]	456	1		T1	4		T3	4		T5	16
valid_sources[0x4d]	410	1		T1	5		T3	16		T4	2
valid_sources[0x4e]	314	1		T1	2		T3	8		T5	12
valid_sources[0x4f]	474	1		T1	3		T3	15		T4	3
valid_sources[0x50]	612	1		T3	5		T4	5		T5	6
valid_sources[0x51]	545	1		T1	4		T3	11		T4	1
valid_sources[0x52]	484	1		T1	2		T3	4		T4	6
valid_sources[0x53]	403	1		T1	1		T3	22		T4	3
valid_sources[0x54]	792	1		T1	5		T2	1		T3	29
valid_sources[0x55]	372	1		T1	3		T3	5		T4	1
valid_sources[0x56]	392	1		T1	1		T3	19		T4	2
valid_sources[0x57]	636	1		T1	5		T3	8		T4	7
valid_sources[0x58]	413	1		T1	1		T2	5		T3	16
valid_sources[0x59]	455	1		T1	2		T3	6		T4	3
valid_sources[0x5a]	472	1		T1	1		T3	3		T4	3
valid_sources[0x5b]	385	1		T1	1		T3	5		T4	1
valid_sources[0x5c]	408	1		T1	2		T3	9		T4	3
valid_sources[0x5d]	446	1		T1	6		T3	7		T4	8
valid_sources[0x5e]	428	1		T1	2		T2	1		T3	2
valid_sources[0x5f]	444	1		T1	5		T3	24		T5	4
valid_sources[0x60]	318	1		T1	2		T3	6		T4	2
valid_sources[0x61]	498	1		T1	1		T3	13		T4	2
valid_sources[0x62]	534	1		T1	2		T3	14		T4	3
valid_sources[0x63]	757	1		T1	1		T3	12		T4	3
valid_sources[0x64]	485	1		T1	5		T3	23		T4	3
valid_sources[0x65]	407	1		T1	5		T3	6		T4	1
valid_sources[0x66]	353	1		T1	2		T3	11		T4	1
valid_sources[0x67]	699	1		T1	1		T3	4		T4	3
valid_sources[0x68]	449	1		T1	4		T3	9		T4	1
valid_sources[0x69]	333	1		T1	6		T3	3		T4	2
valid_sources[0x6a]	572	1		T1	4		T3	6		T4	3
valid_sources[0x6b]	450	1		T1	2		T3	4		T4	2
valid_sources[0x6c]	632	1		T3	3		T4	2		T5	11
valid_sources[0x6d]	504	1		T1	7		T2	1		T3	13
valid_sources[0x6e]	402	1		T1	4		T3	10		T4	1
valid_sources[0x6f]	323	1		T1	1		T3	4		T4	2
valid_sources[0x70]	323	1		T1	1		T3	15		T4	2
valid_sources[0x71]	1864	1		T1	10		T3	3		T4	1
valid_sources[0x72]	378	1		T1	1		T3	10		T4	5
valid_sources[0x73]	500	1		T1	2		T3	10		T4	5
valid_sources[0x74]	553	1		T1	1		T3	15		T4	1
valid_sources[0x75]	500	1		T1	5		T3	10		T4	1
valid_sources[0x76]	523	1		T1	1		T3	13		T4	1
valid_sources[0x77]	282	1		T1	6		T3	12		T4	3
valid_sources[0x78]	875	1		T1	7		T3	9		T4	5
valid_sources[0x79]	401	1		T3	7		T4	1		T7	2
valid_sources[0x7a]	503	1		T1	3		T3	9		T5	9
valid_sources[0x7b]	313	1		T1	3		T3	14		T5	8
valid_sources[0x7c]	450	1		T1	3		T3	3		T4	3
valid_sources[0x7d]	332	1		T1	1		T2	1		T3	8
valid_sources[0x7e]	498	1		T1	1		T2	1		T3	17
valid_sources[0x7f]	388	1		T1	4		T2	1		T3	7
valid_sources[0x80]	410	1		T1	1		T3	18		T4	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24445

1

T1

456

T2

10

T3

717

values[0x0]

all_enables

biggest_size

19241

1

T1

135

T2

7

T3

493

values[0x1]

all_enables

biggest_size

16827

1

T1

145

T2

7

T3

275