Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	77597	1		T2	16		T3	1406		T4	244
full_word	61764	1		T1	736		T2	24		T3	1485

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	139031	1		T1	736		T2	40		T3	2891
auto[TlIntgErrCmd]	102	1		T5	7		T23	3		T62	1
auto[TlIntgErrData]	113	1		T5	5		T23	2		T62	3
auto[TlIntgErrBoth]	115	1		T5	8		T23	5		T62	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	77596	1		T1	456		T2	20		T3	1446
auto[1]	61765	1		T1	280		T2	20		T3	1445

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	52787	1		T2	10		T3	729		T4	206
auto[TlIntgErrNone]	partial	auto[1]	24506	1		T2	6		T3	677		T4	38
auto[TlIntgErrNone]	full_word	auto[0]	24663	1		T1	456		T2	10		T3	717
auto[TlIntgErrNone]	full_word	auto[1]	37075	1		T1	280		T2	14		T3	768
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T5	3		T46	3		T60	4
auto[TlIntgErrCmd]	partial	auto[1]	60	1		T5	4		T23	3		T62	1
auto[TlIntgErrCmd]	full_word	auto[0]	1	1		T60	1		-	-		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T81	1		T73	1		T83	1
auto[TlIntgErrData]	partial	auto[0]	55	1		T5	2		T23	1		T46	5
auto[TlIntgErrData]	partial	auto[1]	48	1		T5	3		T23	1		T62	3
auto[TlIntgErrData]	full_word	auto[0]	7	1		T60	1		T84	1		T81	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T85	1		T86	1		T87	1
auto[TlIntgErrBoth]	partial	auto[0]	43	1		T5	2		T23	3		T62	4
auto[TlIntgErrBoth]	partial	auto[1]	63	1		T5	6		T23	2		T62	2
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T73	1		T83	1		T82	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T84	1		T83	1		T88	1