Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
22.73	0.00	0.00	90.91		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1868869	13966	0	0
ep_in_enable_rd_A	1868869	3236	0	0
ep_out_enable_rd_A	1868869	3102	0	0
in_iso_rd_A	1868869	3364	0	0
intr_enable_rd_A	1868869	4768	0	0
out_iso_rd_A	1868869	3427	0	0
phy_config_rd_A	1868869	2010	0	0
phy_pins_drive_rd_A	1868869	2690	0	0
rxenable_setup_rd_A	1868869	3259	0	0
set_nak_out_rd_A	1868869	3458	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1868869	13966	0	0
T4	8654	13	0	0
T5	80003	6	0	0
T6	4902	20	0	0
T7	3710	0	0	0
T8	3436	0	0	0
T9	1919	0	0	0
T13	3815	0	0	0
T14	9203	0	0	0
T15	6051	6	0	0
T16	12337	814	0	0
T17	0	16	0	0
T18	0	820	0	0
T19	0	864	0	0
T20	0	545	0	0
T23	0	1	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1868869	3236	0	0
T4	8654	100	0	0
T5	80003	0	0	0
T6	4902	0	0	0
T7	3710	0	0	0
T8	3436	0	0	0
T9	1919	0	0	0
T13	3815	0	0	0
T14	9203	0	0	0
T15	6051	6	0	0
T16	12337	0	0	0
T17	0	73	0	0
T19	0	1	0	0
T23	0	118	0	0
T46	0	420	0	0
T65	0	55	0	0
T66	0	12	0	0
T67	0	66	0	0
T68	0	61	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1868869	3102	0	0
T4	8654	16	0	0
T5	80003	0	0	0
T6	4902	0	0	0
T7	3710	0	0	0
T8	3436	0	0	0
T9	1919	0	0	0
T13	3815	0	0	0
T14	9203	0	0	0
T15	6051	51	0	0
T16	12337	0	0	0
T17	0	11	0	0
T23	0	87	0	0
T46	0	436	0	0
T65	0	11	0	0
T66	0	8	0	0
T67	0	24	0	0
T68	0	55	0	0
T69	0	4	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1868869	3364	0	0
T4	8654	11	0	0
T5	80003	0	0	0
T6	4902	0	0	0
T7	3710	0	0	0
T8	3436	0	0	0
T9	1919	0	0	0
T13	3815	0	0	0
T14	9203	0	0	0
T15	6051	66	0	0
T16	12337	0	0	0
T17	0	79	0	0
T23	0	114	0	0
T46	0	467	0	0
T65	0	72	0	0
T66	0	52	0	0
T67	0	20	0	0
T68	0	56	0	0
T70	0	39	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1868869	4768	0	0
T4	8654	20	0	0
T5	80003	0	0	0
T6	4902	0	0	0
T7	3710	0	0	0
T8	3436	19	0	0
T9	1919	0	0	0
T13	3815	0	0	0
T14	9203	0	0	0
T15	6051	4	0	0
T16	12337	0	0	0
T17	0	44	0	0
T19	0	4	0	0
T23	0	179	0	0
T35	0	11	0	0
T65	0	69	0	0
T71	0	5	0	0
T72	0	8	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1868869	3427	0	0
T4	8654	76	0	0
T5	80003	0	0	0
T6	4902	0	0	0
T7	3710	0	0	0
T8	3436	0	0	0
T9	1919	0	0	0
T13	3815	0	0	0
T14	9203	0	0	0
T15	6051	48	0	0
T16	12337	0	0	0
T17	0	30	0	0
T23	0	102	0	0
T46	0	470	0	0
T65	0	17	0	0
T66	0	52	0	0
T67	0	21	0	0
T68	0	52	0	0
T70	0	46	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1868869	2010	0	0
T4	8654	25	0	0
T5	80003	0	0	0
T6	4902	0	0	0
T7	3710	0	0	0
T8	3436	0	0	0
T9	1919	0	0	0
T13	3815	0	0	0
T14	9203	0	0	0
T15	6051	20	0	0
T16	12337	0	0	0
T23	0	37	0	0
T46	0	254	0	0
T65	0	27	0	0
T66	0	10	0	0
T67	0	33	0	0
T68	0	9	0	0
T70	0	10	0	0
T73	0	242	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1868869	2690	0	0
T4	8654	48	0	0
T5	80003	0	0	0
T6	4902	0	0	0
T7	3710	0	0	0
T8	3436	0	0	0
T9	1919	0	0	0
T13	3815	0	0	0
T14	9203	0	0	0
T15	6051	31	0	0
T16	12337	0	0	0
T17	0	14	0	0
T23	0	72	0	0
T46	0	343	0	0
T65	0	42	0	0
T66	0	11	0	0
T67	0	31	0	0
T68	0	4	0	0
T74	0	4	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1868869	3259	0	0
T4	8654	16	0	0
T5	80003	0	0	0
T6	4902	0	0	0
T7	3710	0	0	0
T8	3436	0	0	0
T9	1919	0	0	0
T13	3815	0	0	0
T14	9203	0	0	0
T15	6051	17	0	0
T16	12337	0	0	0
T17	0	46	0	0
T23	0	148	0	0
T46	0	492	0	0
T65	0	54	0	0
T66	0	2	0	0
T67	0	60	0	0
T68	0	46	0	0
T70	0	4	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1868869	3458	0	0
T4	8654	51	0	0
T5	80003	0	0	0
T6	4902	0	0	0
T7	3710	0	0	0
T8	3436	0	0	0
T9	1919	0	0	0
T13	3815	0	0	0
T14	9203	0	0	0
T15	6051	5	0	0
T16	12337	0	0	0
T17	0	3	0	0
T23	0	69	0	0
T42	0	2	0	0
T46	0	526	0	0
T65	0	58	0	0
T66	0	55	0	0
T67	0	42	0	0
T68	0	47	0	0