Line Coverage for Instance : tb.dut.usbdev_avsetupfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 0 | 0.00 |
ALWAYS | 69 | 4 | 0 | 0.00 |
CONT_ASSIGN | 81 | 1 | 0 | 0.00 |
CONT_ASSIGN | 82 | 1 | 0 | 0.00 |
CONT_ASSIGN | 100 | 1 | 0 | 0.00 |
CONT_ASSIGN | 101 | 1 | 0 | 0.00 |
CONT_ASSIGN | 120 | 1 | 0 | 0.00 |
ALWAYS | 123 | 2 | 0 | 0.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 0 | 0.00 |
CONT_ASSIGN | 140 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
0 |
1 |
70 |
0 |
1 |
71 |
0 |
1 |
72 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
81 |
0 |
1 |
82 |
0 |
1 |
100 |
0 |
1 |
101 |
0 |
1 |
120 |
0 |
1 |
123 |
0 |
1 |
124 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
133 |
0 |
1 |
134 |
0 |
1 |
140 |
0 |
1 |
Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo
| Total | Covered | Percent |
Conditions | 14 | 0 | 0.00 |
Logical | 14 | 0 | 0.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
0 |
0.00 |
IF |
69 |
3 |
0 |
0.00 |
IF |
123 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Not Covered |
|
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.usbdev_avoutfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 0 | 0.00 |
ALWAYS | 69 | 4 | 0 | 0.00 |
CONT_ASSIGN | 81 | 1 | 0 | 0.00 |
CONT_ASSIGN | 82 | 1 | 0 | 0.00 |
CONT_ASSIGN | 100 | 1 | 0 | 0.00 |
CONT_ASSIGN | 101 | 1 | 0 | 0.00 |
CONT_ASSIGN | 120 | 1 | 0 | 0.00 |
ALWAYS | 123 | 2 | 0 | 0.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 0 | 0.00 |
CONT_ASSIGN | 140 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
0 |
1 |
70 |
0 |
1 |
71 |
0 |
1 |
72 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
81 |
0 |
1 |
82 |
0 |
1 |
100 |
0 |
1 |
101 |
0 |
1 |
120 |
0 |
1 |
123 |
0 |
1 |
124 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
133 |
0 |
1 |
134 |
0 |
1 |
140 |
0 |
1 |
Cond Coverage for Instance : tb.dut.usbdev_avoutfifo
| Total | Covered | Percent |
Conditions | 14 | 0 | 0.00 |
Logical | 14 | 0 | 0.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
Branch Coverage for Instance : tb.dut.usbdev_avoutfifo
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
0 |
0.00 |
IF |
69 |
3 |
0 |
0.00 |
IF |
123 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Not Covered |
|
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.usbdev_rxfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 0 | 0.00 |
ALWAYS | 69 | 4 | 0 | 0.00 |
CONT_ASSIGN | 81 | 1 | 0 | 0.00 |
CONT_ASSIGN | 82 | 1 | 0 | 0.00 |
CONT_ASSIGN | 100 | 1 | 0 | 0.00 |
CONT_ASSIGN | 101 | 1 | 0 | 0.00 |
CONT_ASSIGN | 120 | 1 | 0 | 0.00 |
ALWAYS | 123 | 2 | 0 | 0.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 0 | 0.00 |
CONT_ASSIGN | 138 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
0 |
1 |
70 |
0 |
1 |
71 |
0 |
1 |
72 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
81 |
0 |
1 |
82 |
0 |
1 |
100 |
0 |
1 |
101 |
0 |
1 |
120 |
0 |
1 |
123 |
0 |
1 |
124 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
133 |
0 |
1 |
134 |
0 |
1 |
138 |
0 |
1 |
Cond Coverage for Instance : tb.dut.usbdev_rxfifo
| Total | Covered | Percent |
Conditions | 16 | 0 | 0.00 |
Logical | 16 | 0 | 0.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
Branch Coverage for Instance : tb.dut.usbdev_rxfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
0 |
0.00 |
TERNARY |
138 |
2 |
0 |
0.00 |
IF |
69 |
3 |
0 |
0.00 |
IF |
123 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Not Covered |
|
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
350403 |
0 |
0 |
T1 |
10902 |
6696 |
0 |
0 |
T2 |
1603 |
40 |
0 |
0 |
T3 |
17768 |
13092 |
0 |
0 |
T4 |
8654 |
1597 |
0 |
0 |
T5 |
80003 |
6781 |
0 |
0 |
T6 |
4902 |
2199 |
0 |
0 |
T7 |
3710 |
40 |
0 |
0 |
T8 |
3436 |
40 |
0 |
0 |
T9 |
1919 |
22 |
0 |
0 |
T14 |
9203 |
1119 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
175 |
175 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
291526 |
0 |
0 |
T1 |
10902 |
736 |
0 |
0 |
T2 |
1603 |
40 |
0 |
0 |
T3 |
17768 |
2891 |
0 |
0 |
T4 |
8654 |
3415 |
0 |
0 |
T5 |
80003 |
2579 |
0 |
0 |
T6 |
4902 |
1103 |
0 |
0 |
T7 |
3710 |
40 |
0 |
0 |
T8 |
3436 |
188 |
0 |
0 |
T9 |
1919 |
22 |
0 |
0 |
T14 |
9203 |
1028 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
175 |
175 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
38366 |
0 |
0 |
T4 |
8654 |
847 |
0 |
0 |
T5 |
80003 |
0 |
0 |
0 |
T6 |
4902 |
1417 |
0 |
0 |
T7 |
3710 |
0 |
0 |
0 |
T8 |
3436 |
0 |
0 |
0 |
T9 |
1919 |
0 |
0 |
0 |
T13 |
3815 |
0 |
0 |
0 |
T14 |
9203 |
0 |
0 |
0 |
T15 |
6051 |
448 |
0 |
0 |
T16 |
12337 |
618 |
0 |
0 |
T17 |
0 |
496 |
0 |
0 |
T18 |
0 |
561 |
0 |
0 |
T19 |
0 |
460 |
0 |
0 |
T20 |
0 |
210 |
0 |
0 |
T21 |
0 |
184 |
0 |
0 |
T22 |
0 |
142 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
175 |
175 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
55807 |
0 |
0 |
T4 |
8654 |
2058 |
0 |
0 |
T5 |
80003 |
0 |
0 |
0 |
T6 |
4902 |
766 |
0 |
0 |
T7 |
3710 |
0 |
0 |
0 |
T8 |
3436 |
0 |
0 |
0 |
T9 |
1919 |
0 |
0 |
0 |
T13 |
3815 |
0 |
0 |
0 |
T14 |
9203 |
0 |
0 |
0 |
T15 |
6051 |
1022 |
0 |
0 |
T16 |
12337 |
596 |
0 |
0 |
T17 |
0 |
910 |
0 |
0 |
T18 |
0 |
538 |
0 |
0 |
T19 |
0 |
1690 |
0 |
0 |
T20 |
0 |
195 |
0 |
0 |
T21 |
0 |
174 |
0 |
0 |
T22 |
0 |
131 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
175 |
175 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
301441 |
0 |
0 |
T1 |
10902 |
6696 |
0 |
0 |
T2 |
1603 |
40 |
0 |
0 |
T3 |
17768 |
13092 |
0 |
0 |
T4 |
8654 |
536 |
0 |
0 |
T5 |
80003 |
6781 |
0 |
0 |
T6 |
4902 |
553 |
0 |
0 |
T7 |
3710 |
40 |
0 |
0 |
T8 |
3436 |
40 |
0 |
0 |
T9 |
1919 |
22 |
0 |
0 |
T14 |
9203 |
1119 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
175 |
175 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 4 | 4 | 100.00 |
CONT_ASSIGN | 44 | 1 | 1 | 100.00 |
CONT_ASSIGN | 45 | 1 | 1 | 100.00 |
CONT_ASSIGN | 48 | 1 | 1 | 100.00 |
CONT_ASSIGN | 49 | 1 | 1 | 100.00 |
CONT_ASSIGN | 53 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
44 |
1 |
1 |
45 |
1 |
1 |
48 |
1 |
1 |
49 |
1 |
1 |
53 |
|
unreachable |
Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
235719 |
0 |
0 |
T1 |
10902 |
736 |
0 |
0 |
T2 |
1603 |
40 |
0 |
0 |
T3 |
17768 |
2891 |
0 |
0 |
T4 |
8654 |
1357 |
0 |
0 |
T5 |
80003 |
2579 |
0 |
0 |
T6 |
4902 |
337 |
0 |
0 |
T7 |
3710 |
40 |
0 |
0 |
T8 |
3436 |
188 |
0 |
0 |
T9 |
1919 |
22 |
0 |
0 |
T14 |
9203 |
1028 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1868869 |
1818774 |
0 |
0 |
T1 |
10902 |
10817 |
0 |
0 |
T2 |
1603 |
1538 |
0 |
0 |
T3 |
17768 |
17695 |
0 |
0 |
T4 |
8654 |
7745 |
0 |
0 |
T5 |
80003 |
78479 |
0 |
0 |
T6 |
4902 |
4083 |
0 |
0 |
T7 |
3710 |
3614 |
0 |
0 |
T8 |
3436 |
3366 |
0 |
0 |
T9 |
1919 |
1858 |
0 |
0 |
T14 |
9203 |
9140 |
0 |
0 |
gen_passthru_fifo.paramCheckPass
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
175 |
175 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T14 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 0 | 0.00 |
ALWAYS | 69 | 4 | 0 | 0.00 |
CONT_ASSIGN | 81 | 1 | 0 | 0.00 |
CONT_ASSIGN | 82 | 1 | 0 | 0.00 |
CONT_ASSIGN | 100 | 1 | 0 | 0.00 |
CONT_ASSIGN | 101 | 1 | 0 | 0.00 |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 2 | 0 | 0.00 |
CONT_ASSIGN | 116 | 1 | 0 | 0.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 0 | 0.00 |
CONT_ASSIGN | 138 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
0 |
1 |
70 |
0 |
1 |
71 |
0 |
1 |
72 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
81 |
0 |
1 |
82 |
0 |
1 |
100 |
0 |
1 |
101 |
0 |
1 |
108 |
0 |
1 |
111 |
0 |
1 |
112 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
116 |
0 |
1 |
133 |
0 |
1 |
134 |
0 |
1 |
138 |
0 |
1 |
Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
| Total | Covered | Percent |
Conditions | 16 | 0 | 0.00 |
Logical | 16 | 0 | 0.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
0 |
0.00 |
TERNARY |
138 |
2 |
0 |
0.00 |
IF |
69 |
3 |
0 |
0.00 |
IF |
123 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Not Covered |
|
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 0 | 0.00 |
ALWAYS | 69 | 4 | 0 | 0.00 |
CONT_ASSIGN | 81 | 1 | 0 | 0.00 |
CONT_ASSIGN | 82 | 1 | 0 | 0.00 |
CONT_ASSIGN | 100 | 1 | 0 | 0.00 |
CONT_ASSIGN | 101 | 1 | 0 | 0.00 |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 2 | 0 | 0.00 |
CONT_ASSIGN | 116 | 1 | 0 | 0.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 0 | 0.00 |
CONT_ASSIGN | 138 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
0 |
1 |
70 |
0 |
1 |
71 |
0 |
1 |
72 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
81 |
0 |
1 |
82 |
0 |
1 |
100 |
0 |
1 |
101 |
0 |
1 |
108 |
0 |
1 |
111 |
0 |
1 |
112 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
116 |
0 |
1 |
133 |
0 |
1 |
134 |
0 |
1 |
138 |
0 |
1 |
Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
| Total | Covered | Percent |
Conditions | 16 | 0 | 0.00 |
Logical | 16 | 0 | 0.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
0 |
0.00 |
TERNARY |
138 |
2 |
0 |
0.00 |
IF |
69 |
3 |
0 |
0.00 |
IF |
123 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Not Covered |
|
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 123 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 0 | 0.00 |
ALWAYS | 69 | 4 | 0 | 0.00 |
CONT_ASSIGN | 81 | 1 | 0 | 0.00 |
CONT_ASSIGN | 82 | 1 | 0 | 0.00 |
CONT_ASSIGN | 100 | 1 | 0 | 0.00 |
CONT_ASSIGN | 101 | 1 | 0 | 0.00 |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 2 | 0 | 0.00 |
CONT_ASSIGN | 116 | 1 | 0 | 0.00 |
CONT_ASSIGN | 130 | 1 | 0 | 0.00 |
CONT_ASSIGN | 131 | 1 | 0 | 0.00 |
CONT_ASSIGN | 138 | 1 | 0 | 0.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
0 |
1 |
70 |
0 |
1 |
71 |
0 |
1 |
72 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
81 |
0 |
1 |
82 |
0 |
1 |
100 |
0 |
1 |
101 |
0 |
1 |
108 |
0 |
1 |
111 |
0 |
1 |
112 |
0 |
1 |
|
|
|
==> MISSING_ELSE |
116 |
0 |
1 |
130 |
0 |
1 |
131 |
0 |
1 |
138 |
0 |
1 |
Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
| Total | Covered | Percent |
Conditions | 24 | 0 | 0.00 |
Logical | 24 | 0 | 0.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Not Covered | |
Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
0 |
0.00 |
TERNARY |
130 |
2 |
0 |
0.00 |
TERNARY |
138 |
2 |
0 |
0.00 |
IF |
69 |
3 |
0 |
0.00 |
IF |
111 |
2 |
0 |
0.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 130 ((gen_normal_fifo.fifo_empty && wvalid_i)) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
LineNo. Expression
-1-: 138 (gen_normal_fifo.empty) ?
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|
LineNo. Expression
-1-: 69 if ((!rst_ni))
-2-: 71 if (gen_normal_fifo.under_rst)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Not Covered |
|
0 |
1 |
Not Covered |
|
0 |
0 |
Not Covered |
|
LineNo. Expression
-1-: 111 if (gen_normal_fifo.fifo_incr_wptr)
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Not Covered |
|