Module Definition
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Module : prim_ram_1p_adv
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_no_stubbed_memory.u_memory_1p 0.00 0.00 0.00



Module Instance : tb.dut.gen_no_stubbed_memory.u_memory_1p

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
22.73 0.00 0.00 90.91 0.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_mem 0.00 0.00 0.00
u_req_d_buf 0.00 0.00
u_write_d_buf 0.00 0.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_ram_1p_adv
Line No.TotalCoveredPercent
TOTAL2300.00
CONT_ASSIGN102100.00
CONT_ASSIGN103100.00
CONT_ASSIGN123100.00
ALWAYS126300.00
CONT_ASSIGN133100.00
CONT_ASSIGN134100.00
CONT_ASSIGN135100.00
CONT_ASSIGN136100.00
CONT_ASSIGN137100.00
CONT_ASSIGN13800
CONT_ASSIGN147100.00
CONT_ASSIGN156100.00
CONT_ASSIGN24800
CONT_ASSIGN249100.00
CONT_ASSIGN251100.00
CONT_ASSIGN255100.00
CONT_ASSIGN310100.00
CONT_ASSIGN311100.00
CONT_ASSIGN312100.00
CONT_ASSIGN313100.00
CONT_ASSIGN31400
CONT_ASSIGN353100.00
CONT_ASSIGN354100.00
CONT_ASSIGN35600
CONT_ASSIGN359100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
102 0 1
103 0 1
123 0 1
126 0 1
127 0 1
129 0 1
133 0 1
134 0 1
135 0 1
136 0 1
137 0 1
138 unreachable
147 0 1
156 0 1
248 unreachable
249 0 1
251 0 1
255 0 1
310 0 1
311 0 1
312 0 1
313 0 1
314 unreachable
353 0 1
354 0 1
356 unreachable
359 0 1


Branch Coverage for Module : prim_ram_1p_adv
Line No.TotalCoveredPercent
Branches 2 0 0.00
IF 126 2 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv' or '../src/lowrisc_prim_ram_1p_adv_0.1/rtl/prim_ram_1p_adv.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 126 if ((!rst_ni))

Branches:
-1-StatusTests
1 Not Covered
0 Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%