Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	62834	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	64558	1		T1	745		T2	378		T3	22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	78287	1		T1	677		T2	360		T3	20
values[0x0]	24081	1		T1	340		T2	166		T3	8
values[0x1]	25024	1		T1	337		T2	170		T3	12

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	43149	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	84243	1		T1	1041		T2	535		T3	29

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	434	1		T1	2		T2	4		T6	5
valid_sources[0x01]	438	1		T1	2		T2	3		T6	2
valid_sources[0x02]	598	1		T1	1		T2	2		T6	4
valid_sources[0x03]	665	1		T1	13		T2	3		T6	2
valid_sources[0x04]	469	1		T1	1		T2	6		T6	5
valid_sources[0x05]	465	1		T1	4		T2	1		T6	3
valid_sources[0x06]	412	1		T2	1		T6	5		T4	4
valid_sources[0x07]	420	1		T2	1		T6	2		T4	6
valid_sources[0x08]	423	1		T1	6		T2	1		T6	5
valid_sources[0x09]	669	1		T1	1		T2	1		T6	3
valid_sources[0x0a]	479	1		T1	2		T2	1		T6	3
valid_sources[0x0b]	468	1		T1	6		T2	7		T6	4
valid_sources[0x0c]	463	1		T1	2		T2	3		T6	3
valid_sources[0x0d]	553	1		T1	6		T2	1		T6	2
valid_sources[0x0e]	552	1		T1	11		T2	3		T6	6
valid_sources[0x0f]	457	1		T1	8		T2	2		T6	2
valid_sources[0x10]	369	1		T1	1		T2	2		T6	5
valid_sources[0x11]	402	1		T1	11		T2	2		T6	3
valid_sources[0x12]	483	1		T1	4		T2	3		T6	3
valid_sources[0x13]	410	1		T1	5		T6	5		T4	1
valid_sources[0x14]	483	1		T1	4		T2	3		T6	4
valid_sources[0x15]	757	1		T1	7		T2	1		T6	2
valid_sources[0x16]	381	1		T1	6		T2	2		T6	8
valid_sources[0x17]	441	1		T1	4		T2	4		T6	4
valid_sources[0x18]	459	1		T1	5		T6	2		T4	2
valid_sources[0x19]	416	1		T1	4		T2	1		T6	1
valid_sources[0x1a]	532	1		T1	5		T2	3		T6	5
valid_sources[0x1b]	543	1		T1	4		T2	1		T6	6
valid_sources[0x1c]	419	1		T1	4		T2	3		T6	1
valid_sources[0x1d]	382	1		T1	1		T4	4		T7	1
valid_sources[0x1e]	478	1		T1	30		T2	2		T6	2
valid_sources[0x1f]	627	1		T1	9		T2	6		T6	4
valid_sources[0x20]	515	1		T1	2		T2	3		T6	4
valid_sources[0x21]	395	1		T1	4		T2	6		T6	1
valid_sources[0x22]	439	1		T1	3		T2	2		T6	2
valid_sources[0x23]	514	1		T1	12		T2	4		T6	6
valid_sources[0x24]	417	1		T1	1		T2	4		T6	2
valid_sources[0x25]	724	1		T2	3		T6	4		T4	5
valid_sources[0x26]	448	1		T1	8		T6	4		T4	5
valid_sources[0x27]	440	1		T1	2		T2	2		T6	1
valid_sources[0x28]	616	1		T1	6		T2	5		T6	4
valid_sources[0x29]	395	1		T1	6		T2	5		T6	1
valid_sources[0x2a]	490	1		T1	1		T2	1		T6	2
valid_sources[0x2b]	549	1		T1	2		T2	3		T6	1
valid_sources[0x2c]	948	1		T1	4		T2	3		T6	3
valid_sources[0x2d]	352	1		T2	3		T6	4		T4	3
valid_sources[0x2e]	564	1		T1	1		T2	1		T6	2
valid_sources[0x2f]	596	1		T1	1		T2	5		T6	2
valid_sources[0x30]	437	1		T6	4		T13	1		T4	2
valid_sources[0x31]	776	1		T1	2		T2	6		T6	1
valid_sources[0x32]	444	1		T1	8		T2	6		T6	3
valid_sources[0x33]	473	1		T1	4		T2	2		T6	5
valid_sources[0x34]	415	1		T1	2		T2	4		T6	8
valid_sources[0x35]	475	1		T1	8		T2	1		T6	4
valid_sources[0x36]	378	1		T1	10		T2	1		T6	1
valid_sources[0x37]	493	1		T1	1		T6	5		T4	6
valid_sources[0x38]	461	1		T1	3		T2	1		T6	7
valid_sources[0x39]	448	1		T1	3		T2	2		T6	6
valid_sources[0x3a]	531	1		T1	12		T2	2		T6	5
valid_sources[0x3b]	483	1		T1	3		T2	2		T6	4
valid_sources[0x3c]	465	1		T2	3		T6	2		T4	1
valid_sources[0x3d]	500	1		T1	12		T2	1		T6	1
valid_sources[0x3e]	604	1		T1	6		T2	1		T4	3
valid_sources[0x3f]	523	1		T1	6		T2	6		T6	7
valid_sources[0x40]	387	1		T1	9		T2	6		T6	5
valid_sources[0x41]	408	1		T1	4		T2	5		T6	2
valid_sources[0x42]	444	1		T1	1		T2	2		T6	2
valid_sources[0x43]	429	1		T1	1		T2	2		T6	3
valid_sources[0x44]	495	1		T1	3		T2	2		T6	3
valid_sources[0x45]	385	1		T1	7		T2	2		T6	2
valid_sources[0x46]	440	1		T1	11		T2	1		T6	5
valid_sources[0x47]	417	1		T1	1		T2	3		T6	2
valid_sources[0x48]	655	1		T1	5		T2	10		T6	1
valid_sources[0x49]	559	1		T2	7		T6	1		T4	4
valid_sources[0x4a]	540	1		T1	6		T2	3		T6	3
valid_sources[0x4b]	786	1		T2	4		T6	1		T4	4
valid_sources[0x4c]	452	1		T1	8		T2	1		T6	1
valid_sources[0x4d]	558	1		T1	8		T2	4		T6	5
valid_sources[0x4e]	447	1		T1	8		T6	3		T4	9
valid_sources[0x4f]	564	1		T1	5		T2	3		T6	2
valid_sources[0x50]	388	1		T1	1		T2	3		T4	4
valid_sources[0x51]	473	1		T1	5		T6	3		T7	5
valid_sources[0x52]	569	1		T1	4		T2	3		T6	2
valid_sources[0x53]	567	1		T1	3		T2	2		T6	2
valid_sources[0x54]	586	1		T1	11		T2	1		T6	4
valid_sources[0x55]	451	1		T1	9		T6	2		T4	4
valid_sources[0x56]	493	1		T1	7		T2	2		T6	1
valid_sources[0x57]	646	1		T1	8		T2	2		T6	1
valid_sources[0x58]	504	1		T1	15		T2	6		T6	1
valid_sources[0x59]	520	1		T1	12		T6	3		T4	2
valid_sources[0x5a]	527	1		T1	1		T6	3		T4	3
valid_sources[0x5b]	441	1		T1	16		T2	5		T6	5
valid_sources[0x5c]	377	1		T6	2		T4	1		T7	5
valid_sources[0x5d]	427	1		T1	3		T2	1		T6	2
valid_sources[0x5e]	562	1		T1	7		T2	2		T6	2
valid_sources[0x5f]	505	1		T1	8		T2	3		T6	1
valid_sources[0x60]	621	1		T1	2		T2	8		T6	4
valid_sources[0x61]	393	1		T2	1		T6	3		T4	1
valid_sources[0x62]	355	1		T2	5		T6	1		T4	5
valid_sources[0x63]	758	1		T1	8		T2	3		T6	3
valid_sources[0x64]	420	1		T1	3		T2	4		T6	2
valid_sources[0x65]	504	1		T2	3		T6	8		T7	2
valid_sources[0x66]	420	1		T1	1		T2	1		T6	1
valid_sources[0x67]	404	1		T2	1		T6	2		T4	7
valid_sources[0x68]	542	1		T1	7		T2	6		T6	4
valid_sources[0x69]	508	1		T1	6		T2	4		T3	11
valid_sources[0x6a]	471	1		T1	8		T6	4		T4	4
valid_sources[0x6b]	396	1		T1	7		T6	1		T7	1
valid_sources[0x6c]	411	1		T1	4		T2	1		T6	2
valid_sources[0x6d]	571	1		T1	8		T2	2		T6	2
valid_sources[0x6e]	536	1		T1	5		T2	3		T6	1
valid_sources[0x6f]	382	1		T1	1		T6	1		T4	1
valid_sources[0x70]	697	1		T1	7		T2	4		T6	7
valid_sources[0x71]	548	1		T1	21		T2	3		T6	1
valid_sources[0x72]	454	1		T2	3		T6	3		T4	3
valid_sources[0x73]	500	1		T2	3		T6	2		T4	1
valid_sources[0x74]	726	1		T1	2		T2	1		T6	1
valid_sources[0x75]	432	1		T1	2		T2	2		T6	3
valid_sources[0x76]	469	1		T1	3		T2	1		T4	4
valid_sources[0x77]	471	1		T1	8		T2	3		T6	4
valid_sources[0x78]	660	1		T1	15		T2	4		T6	1
valid_sources[0x79]	415	1		T1	12		T2	4		T6	6
valid_sources[0x7a]	594	1		T1	6		T2	1		T6	3
valid_sources[0x7b]	501	1		T1	1		T2	4		T6	3
valid_sources[0x7c]	464	1		T1	4		T2	2		T6	4
valid_sources[0x7d]	502	1		T1	3		T2	2		T6	2
valid_sources[0x7e]	524	1		T2	6		T6	2		T4	2
valid_sources[0x7f]	598	1		T1	2		T2	2		T6	6
valid_sources[0x80]	478	1		T1	5		T2	1		T6	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

26085

1

T1

86

T2

56

T3

9

values[0x0]

all_enables

biggest_size

20483

1

T1

335

T2

163

T3

8

values[0x1]

all_enables

biggest_size

17990

1

T1

324

T2

159

T3

5