Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	77093	1		T1	626		T2	327		T3	18
full_word	65494	1		T1	745		T2	378		T3	22

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	142267	1		T1	1371		T2	705		T3	40
auto[TlIntgErrCmd]	89	1		T7	3		T16	1		T25	5
auto[TlIntgErrData]	108	1		T7	4		T16	2		T25	10
auto[TlIntgErrBoth]	123	1		T7	3		T16	7		T25	5

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	80062	1		T1	677		T2	361		T3	20
auto[1]	62525	1		T1	694		T2	344		T3	20

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	53676	1		T1	591		T2	305		T3	11
auto[TlIntgErrNone]	partial	auto[1]	23122	1		T1	35		T2	22		T3	7
auto[TlIntgErrNone]	full_word	auto[0]	26247	1		T1	86		T2	56		T3	9
auto[TlIntgErrNone]	full_word	auto[1]	39222	1		T1	659		T2	322		T3	13
auto[TlIntgErrCmd]	partial	auto[0]	34	1		T7	1		T16	1		T25	2
auto[TlIntgErrCmd]	partial	auto[1]	48	1		T7	1		T25	3		T26	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T56	1		T57	1		T60	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T7	1		T61	1		T57	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T7	1		T16	1		T25	3
auto[TlIntgErrData]	partial	auto[1]	56	1		T7	3		T16	1		T25	7
auto[TlIntgErrData]	full_word	auto[0]	5	1		T56	1		T62	1		T63	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T26	1		T63	1		T64	1
auto[TlIntgErrBoth]	partial	auto[0]	51	1		T7	3		T16	5		T25	3
auto[TlIntgErrBoth]	partial	auto[1]	64	1		T16	2		T25	2		T61	7
auto[TlIntgErrBoth]	full_word	auto[0]	4	1		T56	2		T57	1		T65	1
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T27	2		T57	1		T66	1