Module Definition
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Module Instance : tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 usbdev_avsetupfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 usbdev_avoutfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 usbdev_rxfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 u_reqfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 u_sramreqfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
0.00 0.00 0.00 0.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
0.00 0.00 0.00 0.00 u_rspfifo


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=4,Secure=0,PtrW=2,DepthW=3,WrapPtrW=3 )
Line Coverage for Module self-instances :
SCORELINE
0.00 0.00
tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL2700.00
CONT_ASSIGN41100.00
CONT_ASSIGN42100.00
CONT_ASSIGN46100.00
CONT_ASSIGN47100.00
CONT_ASSIGN51100.00
CONT_ASSIGN52100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
CONT_ASSIGN59100.00
CONT_ASSIGN61100.00
CONT_ASSIGN68100.00
ALWAYS113800.00
ALWAYS125800.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 0 1
42 0 1
46 0 1
47 0 1
51 0 1
52 0 1
55 0 1
56 0 1
59 0 1
61 0 1
68 0 1
113 0 1
114 0 1
115 0 1
116 0 1
117 0 1
118 0 1
119 0 1
120 0 1
==> MISSING_ELSE
125 0 1
126 0 1
127 0 1
128 0 1
129 0 1
130 0 1
131 0 1
132 0 1
==> MISSING_ELSE


Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=8,Secure=0,PtrW=3,DepthW=4,WrapPtrW=4 )
Line Coverage for Module self-instances :
SCORELINE
0.00 0.00
tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
0.00 0.00
tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL2700.00
CONT_ASSIGN41100.00
CONT_ASSIGN42100.00
CONT_ASSIGN46100.00
CONT_ASSIGN47100.00
CONT_ASSIGN51100.00
CONT_ASSIGN52100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
CONT_ASSIGN59100.00
CONT_ASSIGN61100.00
CONT_ASSIGN68100.00
ALWAYS113800.00
ALWAYS125800.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 0 1
42 0 1
46 0 1
47 0 1
51 0 1
52 0 1
55 0 1
56 0 1
59 0 1
61 0 1
68 0 1
113 0 1
114 0 1
115 0 1
116 0 1
117 0 1
118 0 1
119 0 1
120 0 1
==> MISSING_ELSE
125 0 1
126 0 1
127 0 1
128 0 1
129 0 1
130 0 1
131 0 1
132 0 1
==> MISSING_ELSE


Line Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=0,PtrW=1,DepthW=1,WrapPtrW=2 )
Line Coverage for Module self-instances :
SCORELINE
0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORELINE
0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

Line No.TotalCoveredPercent
TOTAL2500.00
CONT_ASSIGN41100.00
CONT_ASSIGN42100.00
CONT_ASSIGN46100.00
CONT_ASSIGN47100.00
CONT_ASSIGN51100.00
CONT_ASSIGN52100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
CONT_ASSIGN59100.00
CONT_ASSIGN61100.00
CONT_ASSIGN68100.00
ALWAYS113700.00
ALWAYS125700.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 0 1
42 0 1
46 0 1
47 0 1
51 0 1
52 0 1
55 0 1
56 0 1
59 0 1
61 0 1
68 0 1
113 0 1
114 0 1
115 0 1
116 unreachable
117 0 1
118 0 1
119 0 1
120 0 1
==> MISSING_ELSE
125 0 1
126 0 1
127 0 1
128 unreachable
129 0 1
130 0 1
131 0 1
132 0 1
==> MISSING_ELSE


Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=4,Secure=0,PtrW=2,DepthW=3,WrapPtrW=3 )
Cond Coverage for Module self-instances :
SCORECOND
0.00 0.00
tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt

TotalCoveredPercent
Conditions2000.00
Logical2000.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 2'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 2'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 2'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 2'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 EXPRESSION (full_o ? (3'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((3'(wptr_o) - 3'(rptr_o))) : (((3'(Depth) - 3'(rptr_o)) + 3'(wptr_o)))))
             ---1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((3'(wptr_o) - 3'(rptr_o))) : (((3'(Depth) - 3'(rptr_o)) + 3'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=8,Secure=0,PtrW=3,DepthW=4,WrapPtrW=4 )
Cond Coverage for Module self-instances :
SCORECOND
0.00 0.00
tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
0.00 0.00
tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt

TotalCoveredPercent
Conditions2000.00
Logical2000.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 3'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 3'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 3'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 3'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 EXPRESSION (full_o ? (4'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o)))))
             ---1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

Cond Coverage for Module : prim_fifo_sync_cnt ( parameter Depth=1,Secure=0,PtrW=1,DepthW=1,WrapPtrW=2 )
Cond Coverage for Module self-instances :
SCORECOND
0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt

SCORECOND
0.00 0.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt

TotalCoveredPercent
Conditions2000.00
Logical2000.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

Branch Coverage for Module : prim_fifo_sync_cnt
Line No.TotalCoveredPercent
Branches 13 0 0.00
TERNARY 68 3 0 0.00
IF 113 5 0 0.00
IF 125 5 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Not Covered
0 1 - - Not Covered
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Not Covered


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Not Covered
0 1 - - Not Covered
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Not Covered

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2700.00
CONT_ASSIGN41100.00
CONT_ASSIGN42100.00
CONT_ASSIGN46100.00
CONT_ASSIGN47100.00
CONT_ASSIGN51100.00
CONT_ASSIGN52100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
CONT_ASSIGN59100.00
CONT_ASSIGN61100.00
CONT_ASSIGN68100.00
ALWAYS113800.00
ALWAYS125800.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 0 1
42 0 1
46 0 1
47 0 1
51 0 1
52 0 1
55 0 1
56 0 1
59 0 1
61 0 1
68 0 1
113 0 1
114 0 1
115 0 1
116 0 1
117 0 1
118 0 1
119 0 1
120 0 1
==> MISSING_ELSE
125 0 1
126 0 1
127 0 1
128 0 1
129 0 1
130 0 1
131 0 1
132 0 1
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2000.00
Logical2000.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 2'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 2'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 2'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 2'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 EXPRESSION (full_o ? (3'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((3'(wptr_o) - 3'(rptr_o))) : (((3'(Depth) - 3'(rptr_o)) + 3'(wptr_o)))))
             ---1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((3'(wptr_o) - 3'(rptr_o))) : (((3'(Depth) - 3'(rptr_o)) + 3'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 0 0.00
TERNARY 68 3 0 0.00
IF 113 5 0 0.00
IF 125 5 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Not Covered
0 1 - - Not Covered
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Not Covered


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Not Covered
0 1 - - Not Covered
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Not Covered

Line Coverage for Instance : tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2700.00
CONT_ASSIGN41100.00
CONT_ASSIGN42100.00
CONT_ASSIGN46100.00
CONT_ASSIGN47100.00
CONT_ASSIGN51100.00
CONT_ASSIGN52100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
CONT_ASSIGN59100.00
CONT_ASSIGN61100.00
CONT_ASSIGN68100.00
ALWAYS113800.00
ALWAYS125800.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 0 1
42 0 1
46 0 1
47 0 1
51 0 1
52 0 1
55 0 1
56 0 1
59 0 1
61 0 1
68 0 1
113 0 1
114 0 1
115 0 1
116 0 1
117 0 1
118 0 1
119 0 1
120 0 1
==> MISSING_ELSE
125 0 1
126 0 1
127 0 1
128 0 1
129 0 1
130 0 1
131 0 1
132 0 1
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2000.00
Logical2000.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 3'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 3'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 3'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 3'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 EXPRESSION (full_o ? (4'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o)))))
             ---1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 0 0.00
TERNARY 68 3 0 0.00
IF 113 5 0 0.00
IF 125 5 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Not Covered
0 1 - - Not Covered
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Not Covered


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Not Covered
0 1 - - Not Covered
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Not Covered

Line Coverage for Instance : tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2700.00
CONT_ASSIGN41100.00
CONT_ASSIGN42100.00
CONT_ASSIGN46100.00
CONT_ASSIGN47100.00
CONT_ASSIGN51100.00
CONT_ASSIGN52100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
CONT_ASSIGN59100.00
CONT_ASSIGN61100.00
CONT_ASSIGN68100.00
ALWAYS113800.00
ALWAYS125800.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 0 1
42 0 1
46 0 1
47 0 1
51 0 1
52 0 1
55 0 1
56 0 1
59 0 1
61 0 1
68 0 1
113 0 1
114 0 1
115 0 1
116 0 1
117 0 1
118 0 1
119 0 1
120 0 1
==> MISSING_ELSE
125 0 1
126 0 1
127 0 1
128 0 1
129 0 1
130 0 1
131 0 1
132 0 1
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2000.00
Logical2000.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 3'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 3'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 3'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 3'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 EXPRESSION (full_o ? (4'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o)))))
             ---1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

Branch Coverage for Instance : tb.dut.usbdev_rxfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 0 0.00
TERNARY 68 3 0 0.00
IF 113 5 0 0.00
IF 125 5 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Not Covered
0 1 - - Not Covered
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Not Covered


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Not Covered
0 1 - - Not Covered
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Not Covered

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2500.00
CONT_ASSIGN41100.00
CONT_ASSIGN42100.00
CONT_ASSIGN46100.00
CONT_ASSIGN47100.00
CONT_ASSIGN51100.00
CONT_ASSIGN52100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
CONT_ASSIGN59100.00
CONT_ASSIGN61100.00
CONT_ASSIGN68100.00
ALWAYS113700.00
ALWAYS125700.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 0 1
42 0 1
46 0 1
47 0 1
51 0 1
52 0 1
55 0 1
56 0 1
59 0 1
61 0 1
68 0 1
113 0 1
114 0 1
115 0 1
116 unreachable
117 0 1
118 0 1
119 0 1
120 0 1
==> MISSING_ELSE
125 0 1
126 0 1
127 0 1
128 unreachable
129 0 1
130 0 1
131 0 1
132 0 1
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2000.00
Logical2000.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 11 0 0.00
TERNARY 68 3 0 0.00
IF 113 4 0 0.00
IF 125 4 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Not Covered
0 1 - - Unreachable
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Not Covered


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Not Covered
0 1 - - Unreachable
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Not Covered

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2500.00
CONT_ASSIGN41100.00
CONT_ASSIGN42100.00
CONT_ASSIGN46100.00
CONT_ASSIGN47100.00
CONT_ASSIGN51100.00
CONT_ASSIGN52100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
CONT_ASSIGN59100.00
CONT_ASSIGN61100.00
CONT_ASSIGN68100.00
ALWAYS113700.00
ALWAYS125700.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 0 1
42 0 1
46 0 1
47 0 1
51 0 1
52 0 1
55 0 1
56 0 1
59 0 1
61 0 1
68 0 1
113 0 1
114 0 1
115 0 1
116 unreachable
117 0 1
118 0 1
119 0 1
120 0 1
==> MISSING_ELSE
125 0 1
126 0 1
127 0 1
128 unreachable
129 0 1
130 0 1
131 0 1
132 0 1
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2000.00
Logical2000.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 11 0 0.00
TERNARY 68 3 0 0.00
IF 113 4 0 0.00
IF 125 4 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Not Covered
0 1 - - Unreachable
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Not Covered


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Not Covered
0 1 - - Unreachable
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Not Covered

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2500.00
CONT_ASSIGN41100.00
CONT_ASSIGN42100.00
CONT_ASSIGN46100.00
CONT_ASSIGN47100.00
CONT_ASSIGN51100.00
CONT_ASSIGN52100.00
CONT_ASSIGN55100.00
CONT_ASSIGN56100.00
CONT_ASSIGN59100.00
CONT_ASSIGN61100.00
CONT_ASSIGN68100.00
ALWAYS113700.00
ALWAYS125700.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 0 1
42 0 1
46 0 1
47 0 1
51 0 1
52 0 1
55 0 1
56 0 1
59 0 1
61 0 1
68 0 1
113 0 1
114 0 1
115 0 1
116 unreachable
117 0 1
118 0 1
119 0 1
120 0 1
==> MISSING_ELSE
125 0 1
126 0 1
127 0 1
128 unreachable
129 0 1
130 0 1
131 0 1
132 0 1
==> MISSING_ELSE


Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2000.00
Logical2000.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       51
 SUB-EXPRESSION (wptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 1'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       52
 SUB-EXPRESSION (rptr_o == 1'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 EXPRESSION (full_o ? (1'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o)))))
             ---1--
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((1'(wptr_o) - 1'(rptr_o))) : (((1'(Depth) - 1'(rptr_o)) + 1'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0Not Covered
1Not Covered

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 11 0 0.00
TERNARY 68 3 0 0.00
IF 113 4 0 0.00
IF 125 4 0 0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Not Covered
0 0 Not Covered


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Not Covered
0 1 - - Unreachable
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Not Covered


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Not Covered
0 1 - - Unreachable
0 0 1 - Not Covered
0 0 0 1 Not Covered
0 0 0 0 Not Covered

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%