Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
22.16	0.00	0.00	88.64		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	2064233	11881	0	0
ep_in_enable_rd_A	2064233	3551	0	0
ep_out_enable_rd_A	2064233	3369	0	0
in_iso_rd_A	2064233	3467	0	0
intr_enable_rd_A	2064233	4827	0	0
out_iso_rd_A	2064233	3414	0	0
phy_config_rd_A	2064233	2220	0	0
phy_pins_drive_rd_A	2064233	3044	0	0
rxenable_setup_rd_A	2064233	3071	0	0
set_nak_out_rd_A	2064233	3263	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064233	11881	0	0
T1	5837	22	0	0
T2	7021	10	0	0
T3	2075	0	0	0
T4	10078	0	0	0
T5	2312	0	0	0
T6	8643	0	0	0
T7	46670	1	0	0
T12	2016	0	0	0
T13	1841	0	0	0
T16	24596	3	0	0
T17	0	17	0	0
T18	0	6	0	0
T19	0	834	0	0
T20	0	11	0	0
T21	0	295	0	0
T25	0	5	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064233	3551	0	0
T4	10078	49	0	0
T5	2312	0	0	0
T6	8643	81	0	0
T7	46670	139	0	0
T11	0	2	0	0
T12	2016	0	0	0
T13	1841	0	0	0
T14	2305	0	0	0
T15	2867	0	0	0
T16	24596	0	0	0
T18	0	48	0	0
T23	0	46	0	0
T26	0	192	0	0
T28	1698	0	0	0
T30	0	80	0	0
T32	0	21	0	0
T47	0	231	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064233	3369	0	0
T4	10078	36	0	0
T5	2312	0	0	0
T6	8643	63	0	0
T7	46670	256	0	0
T12	2016	0	0	0
T13	1841	0	0	0
T14	2305	0	0	0
T15	2867	0	0	0
T16	24596	0	0	0
T18	0	4	0	0
T23	0	49	0	0
T26	0	247	0	0
T28	1698	0	0	0
T30	0	11	0	0
T32	0	17	0	0
T34	0	208	0	0
T47	0	249	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064233	3467	0	0
T4	10078	26	0	0
T5	2312	0	0	0
T6	8643	17	0	0
T7	46670	294	0	0
T11	0	3	0	0
T12	2016	0	0	0
T13	1841	0	0	0
T14	2305	0	0	0
T15	2867	0	0	0
T16	24596	0	0	0
T18	0	42	0	0
T23	0	24	0	0
T26	0	225	0	0
T28	1698	0	0	0
T30	0	109	0	0
T32	0	45	0	0
T47	0	237	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064233	4827	0	0
T3	2075	38	0	0
T4	10078	39	0	0
T5	2312	5	0	0
T6	8643	47	0	0
T7	46670	401	0	0
T12	2016	16	0	0
T13	1841	17	0	0
T14	2305	0	0	0
T15	2867	0	0	0
T16	24596	0	0	0
T18	0	76	0	0
T30	0	102	0	0
T37	0	5	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064233	3414	0	0
T4	10078	48	0	0
T5	2312	0	0	0
T6	8643	77	0	0
T7	46670	174	0	0
T11	0	1	0	0
T12	2016	0	0	0
T13	1841	0	0	0
T14	2305	0	0	0
T15	2867	0	0	0
T16	24596	0	0	0
T18	0	8	0	0
T23	0	36	0	0
T26	0	270	0	0
T28	1698	0	0	0
T30	0	38	0	0
T34	0	180	0	0
T47	0	223	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064233	2220	0	0
T4	10078	35	0	0
T5	2312	0	0	0
T6	8643	39	0	0
T7	46670	94	0	0
T11	0	3	0	0
T12	2016	0	0	0
T13	1841	0	0	0
T14	2305	0	0	0
T15	2867	0	0	0
T16	24596	0	0	0
T18	0	8	0	0
T23	0	23	0	0
T26	0	122	0	0
T28	1698	0	0	0
T30	0	48	0	0
T34	0	212	0	0
T47	0	177	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064233	3044	0	0
T4	10078	85	0	0
T5	2312	0	0	0
T6	8643	31	0	0
T7	46670	297	0	0
T11	0	2	0	0
T12	2016	0	0	0
T13	1841	0	0	0
T14	2305	0	0	0
T15	2867	0	0	0
T16	24596	0	0	0
T18	0	37	0	0
T23	0	16	0	0
T26	0	213	0	0
T28	1698	0	0	0
T30	0	18	0	0
T32	0	22	0	0
T47	0	233	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064233	3071	0	0
T4	10078	59	0	0
T5	2312	0	0	0
T6	8643	65	0	0
T7	46670	180	0	0
T12	2016	0	0	0
T13	1841	0	0	0
T14	2305	0	0	0
T15	2867	0	0	0
T16	24596	0	0	0
T18	0	48	0	0
T23	0	11	0	0
T26	0	217	0	0
T28	1698	0	0	0
T30	0	6	0	0
T32	0	24	0	0
T34	0	196	0	0
T47	0	212	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2064233	3263	0	0
T4	10078	52	0	0
T5	2312	0	0	0
T6	8643	32	0	0
T7	46670	276	0	0
T11	0	4	0	0
T12	2016	0	0	0
T13	1841	0	0	0
T14	2305	0	0	0
T15	2867	0	0	0
T16	24596	0	0	0
T18	0	6	0	0
T23	0	33	0	0
T26	0	248	0	0
T28	1698	0	0	0
T30	0	3	0	0
T32	0	55	0	0
T47	0	272	0	0