Module Definition
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Module : tlul_adapter_sram
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.59 78.81 92.31 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_no_stubbed_memory.u_tlul2sram 92.43 98.59 78.81 92.31 100.00



Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.43 98.59 78.81 92.31 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.96 86.89 75.84 81.11 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.03 97.53 88.06 94.55 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_err 67.62 76.92 68.57 25.00 100.00
u_reqfifo 88.33 95.00 75.00 83.33 100.00
u_rsp_gen 91.67 83.33 100.00
u_rspfifo 89.32 95.00 77.27 85.00 100.00
u_sram_byte 100.00 100.00 100.00
u_sramreqfifo 87.64 95.00 72.22 83.33 100.00
u_tlul_data_integ_enc_data 0.00 0.00
u_tlul_data_integ_enc_instr 0.00 0.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
TOTAL717098.59
CONT_ASSIGN10700
CONT_ASSIGN11400
ALWAYS12933100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN15111100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN27211100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27411100.00
ALWAYS2798787.50
ALWAYS29966100.00
CONT_ASSIGN31311100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN33611100.00
CONT_ASSIGN34111100.00
CONT_ASSIGN34711100.00
CONT_ASSIGN35911100.00
ALWAYS36233100.00
CONT_ASSIGN36911100.00
CONT_ASSIGN39011100.00
CONT_ASSIGN39111100.00
CONT_ASSIGN39211100.00
CONT_ASSIGN39311100.00
ALWAYS42366100.00
ALWAYS43555100.00
CONT_ASSIGN45011100.00
CONT_ASSIGN45111100.00
CONT_ASSIGN45211100.00
CONT_ASSIGN45611100.00
CONT_ASSIGN45711100.00
CONT_ASSIGN45911100.00
CONT_ASSIGN46011100.00
CONT_ASSIGN46711100.00
CONT_ASSIGN47011100.00
CONT_ASSIGN47411100.00
CONT_ASSIGN47511100.00
CONT_ASSIGN47711100.00
CONT_ASSIGN47911100.00
CONT_ASSIGN48611100.00
ALWAYS51733100.00
CONT_ASSIGN52311100.00
CONT_ASSIGN52611100.00
CONT_ASSIGN53111100.00
CONT_ASSIGN53600
CONT_ASSIGN62011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
107 unreachable
114 unreachable
129 1 1
130 1 1
131 1 1
132 unreachable
MISSING_ELSE
138 1 1
144 1 1
151 1 1
176 1 1
188 1 1
272 1 1
273 1 1
274 1 1
279 1 1
281 1 1
282 1 1
284 0 1
285 1 1
286 1 1
289 1 1
292 1 1
299 1 1
301 1 1
302 1 1
303 1 1
305 1 1
308 1 1
313 1 1
317 1 1
336 1 1
341 1 1
347 1 1
359 1 1
362 1 1
363 1 1
365 1 1
369 1 1
390 1 1
391 1 1
392 1 1
393 1 1
423 1 1
424 1 1
426 1 1
427 1 1
428 1 1
429 1 1
MISSING_ELSE
435 1 1
436 1 1
438 1 1
439 1 1
440 1 1
MISSING_ELSE
450 1 1
451 1 1
452 1 1
456 1 1
457 1 1
459 1 1
460 1 1
467 1 1
470 1 1
474 1 1
475 1 1
477 1 1
479 1 1
486 1 1
517 1 1
518 1 1
519 1 1
523 1 1
526 1 1
531 1 1
536 unreachable
620 1 1


Cond Coverage for Module : tlul_adapter_sram
TotalCoveredPercent
Conditions1189378.81
Logical1189378.81
Non-Logical00
Event00

 LINE       114
 EXPRESSION (readback_error | readback_error_q)
             -------1------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10Unreachable

 LINE       131
 EXPRESSION (intg_error || rsp_fifo_error || sramreqfifo_error || reqfifo_error)
             -----1----    -------2------    --------3--------    ------4------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001Unreachable
0010Unreachable
0100Unreachable
1000Unreachable

 LINE       138
 EXPRESSION (intg_error | rsp_fifo_error | sramreqfifo_error | reqfifo_error | intg_error_q)
             -----1----   -------2------   --------3--------   ------4------   ------5-----
-1--2--3--4--5-StatusTests
00000CoveredT1,T2,T3
00001Not Covered
00010Unreachable
00100Unreachable
01000Unreachable
10000Unreachable

 LINE       144
 EXPRESSION 
 Number  Term
      1  ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData)) ? ((ByteAccess == 1'b0) ? ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2)) : 1'b0) : 1'b0)
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))
                 ---------------1--------------    ----------------2----------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutFullData)
                ---------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_opcode == PutPartialData)
                ----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION ((tl_i.a_mask != '1) || (tl_i.a_size != 2'h2))
                 ---------1---------    ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T7,T17
10CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_mask != '1)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 SUB-EXPRESSION (tl_i.a_size != 2'h2)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       176
 EXPRESSION (wr_attr_error | wr_vld_error | rd_vld_error | instr_error | tlul_error | intg_error)
             ------1------   ------2-----   ------3-----   -----4-----   -----5----   -----6----
-1--2--3--4--5--6-StatusTests
000000CoveredT2,T3,T27
000001Unreachable
000010CoveredT1,T2,T3
000100Not Covered
001000Unreachable
010000Unreachable
100000Not Covered

 LINE       272
 EXPRESSION (tl_i_int.a_valid & tl_o_int.a_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T27
11CoveredT2,T3,T27

 LINE       273
 EXPRESSION (tl_o_int.d_valid & tl_i_int.d_ready)
             --------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T17,T19
11CoveredT2,T3,T27

 LINE       274
 EXPRESSION (req_o & gnt_i)
             --1--   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT79,T80,T81
11CoveredT2,T3,T27

 LINE       285
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT2,T3,T23
1CoveredT3,T27,T17

 LINE       302
 EXPRESSION (reqfifo_rdata.op == OpRead)
            --------------1-------------
-1-StatusTests
0CoveredT2,T3,T23
1CoveredT3,T27,T17

 LINE       303
 EXPRESSION (rspfifo_rdata.error | reqfifo_rdata.error)
             ---------1---------   ---------2---------
-1--2-StatusTests
00CoveredT3,T27,T17
01Not Covered
10Not Covered

 LINE       313
 EXPRESSION (d_valid & reqfifo_rvalid & rspfifo_rvalid & (reqfifo_rdata.op == OpRead))
             ---1---   -------2------   -------3------   --------------4-------------
-1--2--3--4-StatusTests
0111Not Covered
1011Not Covered
1101Not Covered
1110Not Covered
1111CoveredT3,T27,T17

 LINE       313
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T27,T17

 LINE       341
 EXPRESSION ((vld_rd_rsp & ((~d_error))) ? rspfifo_rdata.data : error_blanking_data)
             -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T27,T17

 LINE       341
 SUB-EXPRESSION (vld_rd_rsp & ((~d_error)))
                 -----1----   ------2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T27,T17

 LINE       347
 EXPRESSION ((vld_rd_rsp && reqfifo_rdata.error) ? error_blanking_integ : (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp && reqfifo_rdata.error)
                 -----1----    ---------2---------
-1--2-StatusTests
01Not Covered
10CoveredT3,T27,T17
11Not Covered

 LINE       347
 SUB-EXPRESSION (vld_rd_rsp ? rspfifo_rdata.data_intg : prim_secded_pkg::SecdedInv3932ZeroEcc)
                 -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T27,T17

 LINE       359
 EXPRESSION (error_internal & tl_i_int.a_valid & ((~tl_o_int.a_ready)))
             -------1------   --------2-------   ----------3----------
-1--2--3-StatusTests
011CoveredT2,T3,T27
101CoveredT1,T2,T3
110Not Covered
111Not Covered

 LINE       369
 EXPRESSION ((d_valid && (reqfifo_rdata.op != OpRead)) ? AccessAck : AccessAckData)
             --------------------1--------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T23

 LINE       369
 SUB-EXPRESSION (d_valid && (reqfifo_rdata.op != OpRead))
                 ---1---    --------------2-------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T27,T17
11CoveredT2,T3,T23

 LINE       369
 SUB-EXPRESSION (reqfifo_rdata.op != OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.size : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T27

 LINE       369
 EXPRESSION (d_valid ? reqfifo_rdata.source : '0)
             ---1---
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T27

 LINE       369
 EXPRESSION (d_valid && d_error)
             ---1---    ---2---
-1--2-StatusTests
01Not Covered
10CoveredT2,T3,T27
11Not Covered

 LINE       369
 EXPRESSION ((gnt_i | missed_err_gnt_q) & reqfifo_wready & sramreqfifo_wready & sramreqaddrfifo_wready)
             -------------1------------   -------2------   ---------3--------   -----------4----------
-1--2--3--4-StatusTests
0111CoveredT1,T3,T27
1011CoveredT2,T3,T19
1101Not Covered
1110Unreachable
1111CoveredT1,T2,T3

 LINE       369
 SUB-EXPRESSION (gnt_i | missed_err_gnt_q)
                 --1--   --------2-------
-1--2-StatusTests
00CoveredT1,T3,T27
01Not Covered
10CoveredT1,T2,T3

 LINE       390
 EXPRESSION (tl_i_int.a_valid & reqfifo_wready & ((~error_internal)))
             --------1-------   -------2------   ---------3---------
-1--2--3-StatusTests
011Not Covered
101CoveredT2,T3,T27
110Not Covered
111CoveredT2,T3,T27

 LINE       392
 EXPRESSION (tl_i_int.a_valid & (tl_i_int.a_opcode inside {PutFullData, PutPartialData}))
             --------1-------   ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T27,T17
11CoveredT2,T3,T23

 LINE       393
 EXPRESSION (tl_i_int.a_valid ? tl_i_int.a_address[DataBitWidth+:SramAw] : '0)
             --------1-------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT2,T3,T27

 LINE       429
 EXPRESSION ((tl_i_int.a_mask[i] && we_o) ? tl_i_int.a_data[(8 * i)+:8] : '0)
             --------------1-------------
-1-StatusTests
0CoveredT3,T27,T17
1CoveredT2,T3,T23

 LINE       429
 SUB-EXPRESSION (tl_i_int.a_mask[i] && we_o)
                 ---------1--------    --2-
-1--2-StatusTests
01Not Covered
10CoveredT3,T27,T17
11CoveredT2,T3,T23

 LINE       452
 EXPRESSION (((|wmask_intg)) & ((|wdata_intg)))
             -------1-------   -------2-------
-1--2-StatusTests
01Not Covered
10CoveredT3,T20,T46
11CoveredT2,T3,T27

 LINE       460
 EXPRESSION ((tl_i_int.a_opcode != Get) ? OpWrite : OpRead)
             -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       460
 SUB-EXPRESSION (tl_i_int.a_opcode != Get)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       474
 EXPRESSION (sram_ack & ((~we_o)))
             ----1---   ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT2,T3,T23
11CoveredT3,T27,T17

 LINE       477
 EXPRESSION (rvalid_i & reqfifo_rvalid)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT2,T3,T19
10Not Covered
11CoveredT3,T27,T17

 LINE       531
 EXPRESSION (((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error))) ? reqfifo_rready : 1'b0)
             ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T27,T17

 LINE       531
 SUB-EXPRESSION ((reqfifo_rdata.op == OpRead) & ((~reqfifo_rdata.error)))
                 --------------1-------------   ------------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T27,T17

 LINE       531
 SUB-EXPRESSION (reqfifo_rdata.op == OpRead)
                --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T27,T17

Branch Coverage for Module : tlul_adapter_sram
Line No.TotalCoveredPercent
Branches 26 24 92.31
TERNARY 144 2 2 100.00
TERNARY 341 2 2 100.00
TERNARY 347 3 2 66.67
TERNARY 393 2 2 100.00
TERNARY 531 2 2 100.00
IF 129 2 2 100.00
IF 281 4 3 75.00
IF 301 3 3 100.00
IF 362 2 2 100.00
IF 426 2 2 100.00
IF 438 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_adapter_sram.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 144 (((tl_i.a_opcode == PutFullData) || (tl_i.a_opcode == PutPartialData))) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 341 ((vld_rd_rsp & (~d_error))) ?

Branches:
-1-StatusTests
1 Covered T3,T27,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 347 ((vld_rd_rsp && reqfifo_rdata.error)) ? -2-: 347 (vld_rd_rsp) ?

Branches:
-1--2-StatusTests
1 - Not Covered
0 1 Covered T3,T27,T17
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 393 (tl_i_int.a_valid) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T27
0 Covered T1,T2,T3


LineNo. Expression -1-: 531 (((reqfifo_rdata.op == OpRead) & (~reqfifo_rdata.error))) ?

Branches:
-1-StatusTests
1 Covered T3,T27,T17
0 Covered T1,T2,T3


LineNo. Expression -1-: 129 if ((!rst_ni)) -2-: 131 if ((((intg_error || rsp_fifo_error) || sramreqfifo_error) || reqfifo_error))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Unreachable
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 281 if (reqfifo_rvalid) -2-: 282 if (reqfifo_rdata.error) -3-: 285 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2--3-StatusTests
1 1 - Not Covered
1 0 1 Covered T3,T27,T17
1 0 0 Covered T2,T3,T23
0 - - Covered T1,T2,T3


LineNo. Expression -1-: 301 if (reqfifo_rvalid) -2-: 302 if ((reqfifo_rdata.op == OpRead))

Branches:
-1--2-StatusTests
1 1 Covered T3,T27,T17
1 0 Covered T2,T3,T23
0 - Covered T1,T2,T3


LineNo. Expression -1-: 362 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 426 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T2,T3,T27
0 Covered T1,T2,T3


LineNo. Expression -1-: 438 if (tl_i_int.a_valid)

Branches:
-1-StatusTests
1 Covered T2,T3,T27
0 Covered T1,T2,T3


Assert Coverage for Module : tlul_adapter_sram
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 13 13 100.00 13 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 13 13 100.00 13 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AddrOutKnown_A 505334164 505126465 0 0
DataIntgOptions_A 2687 2687 0 0
ReqOutKnown_A 505334164 505126465 0 0
SramDwHasByteGranularity_A 2687 2687 0 0
SramDwIsMultipleOfTlulWidth_A 2687 2687 0 0
TlOutKnownIfFifoKnown_A 505334164 505126465 0 0
TlOutValidKnown_A 505334164 505126465 0 0
WdataOutKnown_A 505334164 505126465 0 0
WeOutKnown_A 505334164 505126465 0 0
WmaskOutKnown_A 505334164 505126465 0 0
adapterNoReadOrWrite 2687 2687 0 0
rvalidHighReqFifoEmpty 505334164 588087 0 0
rvalidHighWhenRspFifoFull 505334164 588087 0 0


AddrOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505334164 505126465 0 0
T1 292332 292278 0 0
T2 16462 16394 0 0
T3 786294 786226 0 0
T6 112052 112044 0 0
T7 169123 169049 0 0
T16 11606 11538 0 0
T17 37391 37297 0 0
T18 156943 156862 0 0
T27 39001 38934 0 0
T28 8179 8097 0 0

DataIntgOptions_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2687 2687 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

ReqOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505334164 505126465 0 0
T1 292332 292278 0 0
T2 16462 16394 0 0
T3 786294 786226 0 0
T6 112052 112044 0 0
T7 169123 169049 0 0
T16 11606 11538 0 0
T17 37391 37297 0 0
T18 156943 156862 0 0
T27 39001 38934 0 0
T28 8179 8097 0 0

SramDwHasByteGranularity_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2687 2687 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

SramDwIsMultipleOfTlulWidth_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2687 2687 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

TlOutKnownIfFifoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505334164 505126465 0 0
T1 292332 292278 0 0
T2 16462 16394 0 0
T3 786294 786226 0 0
T6 112052 112044 0 0
T7 169123 169049 0 0
T16 11606 11538 0 0
T17 37391 37297 0 0
T18 156943 156862 0 0
T27 39001 38934 0 0
T28 8179 8097 0 0

TlOutValidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505334164 505126465 0 0
T1 292332 292278 0 0
T2 16462 16394 0 0
T3 786294 786226 0 0
T6 112052 112044 0 0
T7 169123 169049 0 0
T16 11606 11538 0 0
T17 37391 37297 0 0
T18 156943 156862 0 0
T27 39001 38934 0 0
T28 8179 8097 0 0

WdataOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505334164 505126465 0 0
T1 292332 292278 0 0
T2 16462 16394 0 0
T3 786294 786226 0 0
T6 112052 112044 0 0
T7 169123 169049 0 0
T16 11606 11538 0 0
T17 37391 37297 0 0
T18 156943 156862 0 0
T27 39001 38934 0 0
T28 8179 8097 0 0

WeOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505334164 505126465 0 0
T1 292332 292278 0 0
T2 16462 16394 0 0
T3 786294 786226 0 0
T6 112052 112044 0 0
T7 169123 169049 0 0
T16 11606 11538 0 0
T17 37391 37297 0 0
T18 156943 156862 0 0
T27 39001 38934 0 0
T28 8179 8097 0 0

WmaskOutKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 505334164 505126465 0 0
T1 292332 292278 0 0
T2 16462 16394 0 0
T3 786294 786226 0 0
T6 112052 112044 0 0
T7 169123 169049 0 0
T16 11606 11538 0 0
T17 37391 37297 0 0
T18 156943 156862 0 0
T27 39001 38934 0 0
T28 8179 8097 0 0

adapterNoReadOrWrite
NameAttemptsReal SuccessesFailuresIncomplete
Total 2687 2687 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

rvalidHighReqFifoEmpty
NameAttemptsReal SuccessesFailuresIncomplete
Total 505334164 588087 0 0
T3 786294 122 0 0
T6 112052 0 0 0
T7 169123 0 0 0
T16 11606 0 0 0
T17 37391 80 0 0
T18 156943 0 0 0
T19 45523 208 0 0
T20 65802 146 0 0
T23 0 5 0 0
T27 39001 79 0 0
T28 8179 0 0 0
T38 0 54 0 0
T46 0 7 0 0
T47 0 13 0 0
T73 0 34 0 0

rvalidHighWhenRspFifoFull
NameAttemptsReal SuccessesFailuresIncomplete
Total 505334164 588087 0 0
T3 786294 122 0 0
T6 112052 0 0 0
T7 169123 0 0 0
T16 11606 0 0 0
T17 37391 80 0 0
T18 156943 0 0 0
T19 45523 208 0 0
T20 65802 146 0 0
T23 0 5 0 0
T27 39001 79 0 0
T28 8179 0 0 0
T38 0 54 0 0
T46 0 7 0 0
T47 0 13 0 0
T73 0 34 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%