Module Definition
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Module : tlul_sram_byte
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sram_byte 100.00 100.00 100.00



Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sram_byte

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
92.43 98.59 78.81 92.31 100.00 gen_no_stubbed_memory.u_tlul2sram


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_sram_byte
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN70211100.00
CONT_ASSIGN70311100.00
CONT_ASSIGN70411100.00
CONT_ASSIGN71000
CONT_ASSIGN71600
CONT_ASSIGN71700
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
702 1 1
703 1 1
704 1 1
710 unreachable
716 unreachable
717 unreachable


Assert Coverage for Module : tlul_sram_byte
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
SramReadbackAndIntg 2687 2687 0 0


SramReadbackAndIntg
NameAttemptsReal SuccessesFailuresIncomplete
Total 2687 2687 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T16 1 1 0 0
T17 1 1 0 0
T18 1 1 0 0
T27 1 1 0 0
T28 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%