Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.35	100.00	69.42			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo	90.62	100.00	62.50			100.00	100.00
tb.dut.usbdev_avoutfifo	91.07	100.00	64.29			100.00	100.00
tb.dut.usbdev_rxfifo	92.19	100.00	68.75			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo	92.19	100.00	68.75			100.00	100.00
tb.dut.usbdev_avsetupfifo	92.86	100.00	71.43			100.00	100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo	93.75	100.00	75.00			100.00	100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
92.86	100.00

tb.dut.usbdev_avsetupfifo

SCORE	LINE
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
92.19	100.00

tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORE	LINE
100.00	100.00

tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
90.62	62.50

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T15,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T15,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T15,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T10,T15,T16
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
93.75	75.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T50,T70
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T15,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T15,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T15,T16,T17
1	1	0	Not Covered
1	1	1	Covered	T10,T15,T16

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T15,T16

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T15,T16

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T15,T50,T70
1	0	Covered	T10,T15,T16
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T10,T15,T16
1	Covered	T1,T2,T3

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.86	71.43

tb.dut.usbdev_avsetupfifo

SCORE	COND
91.07	64.29

tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T83
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T46,T47,T48
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T4

---

Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
92.19	68.75

tb.dut.usbdev_rxfifo

SCORE	COND
92.19	68.75

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T10

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T10

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T10
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T4

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T10
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
92.86	100.00

tb.dut.usbdev_avsetupfifo

SCORE	BRANCH
91.07	100.00

tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
93.75	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T10,T15,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T15,T16
0	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
92.19	100.00

tb.dut.usbdev_rxfifo

SCORE	BRANCH
92.19	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCORE	BRANCH
90.62	100.00

tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T10

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T10
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	567770416	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	2147483647	476780609	0	0
gen_passthru_fifo.paramCheckPass	18084	18084	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	567770416	0	0
T1	282159	41992	0	0
T2	88810	436	0	0
T3	84640	1076	0	0
T4	6234912	1703936	0	0
T5	1682664	535580	0	0
T10	88248	774	0	0
T11	114984	1262	0	0
T12	110784	628	0	0
T13	87576	604	0	0
T14	1156632	160608	0	0
T15	25086	610	0	0
T16	825564	254200	0	0
T17	127058	28433	0	0
T18	0	687	0	0
T19	0	305	0	0
T50	0	58436	0	0
T70	0	256586	0	0
T83	0	5516	0	0
T84	0	5478	0	0
T85	0	10	0	0
T86	0	98	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	376212	375420	0	0
T2	106572	105528	0	0
T3	101568	100560	0	0
T4	6234912	6233784	0	0
T5	1682664	1681572	0	0
T10	88248	87168	0	0
T11	114984	113784	0	0
T12	110784	109944	0	0
T13	87576	86640	0	0
T14	1156632	1155432	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	376212	375420	0	0
T2	106572	105528	0	0
T3	101568	100560	0	0
T4	6234912	6233784	0	0
T5	1682664	1681572	0	0
T10	88248	87168	0	0
T11	114984	113784	0	0
T12	110784	109944	0	0
T13	87576	86640	0	0
T14	1156632	1155432	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	376212	375420	0	0
T2	106572	105528	0	0
T3	101568	100560	0	0
T4	6234912	6233784	0	0
T5	1682664	1681572	0	0
T10	88248	87168	0	0
T11	114984	113784	0	0
T12	110784	109944	0	0
T13	87576	86640	0	0
T14	1156632	1155432	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	476780609	0	0
T1	94053	41752	0	0
T2	35524	310	0	0
T3	33856	1036	0	0
T4	3117456	1025328	0	0
T5	841332	268540	0	0
T10	44124	714	0	0
T11	57492	1202	0	0
T12	55392	576	0	0
T13	43788	568	0	0
T14	578316	0	0	0
T15	25086	595	0	0
T16	825564	246408	0	0
T17	127058	28231	0	0
T18	0	627	0	0
T19	0	183	0	0
T50	0	34190	0	0
T70	0	165564	0	0
T81	0	111361	0	0
T83	0	5516	0	0
T84	0	5478	0	0
T85	0	6	0	0
T86	0	98	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	18084	18084	0	0
T1	6	6	0	0
T2	6	6	0	0
T3	6	6	0	0
T4	6	6	0	0
T5	6	6	0	0
T10	6	6	0	0
T11	6	6	0	0
T12	6	6	0	0
T13	6	6	0	0
T14	6	6	0	0