Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.86	100.00	71.43			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.06	100.00	88.24			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.29	94.44	81.34	92.73		97.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.07	100.00	64.29			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	100.00	85.29			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.29	94.44	81.34	92.73		97.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.53	100.00	86.11			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.29	94.44	81.34	92.73		97.92	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.43	98.59	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.62	100.00	62.50			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.64	95.00	72.22			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.43	98.59	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.75	100.00	75.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.32	95.00	77.27			85.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.43	98.59	78.81			92.31	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	14	10	71.43
Logical	14	10	71.43
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T83
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T4,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T46,T47,T48
1	1	0	Not Covered
1	1	1	Covered	T1,T4,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T4,T12
1	1	0	Not Covered
1	1	1	Covered	T4,T12,T13

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T12
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375709729	141599550	0	0
DepthKnown_A	375709729	375490852	0	0
RvalidKnown_A	375709729	375490852	0	0
WreadyKnown_A	375709729	375490852	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	375709729	141599550	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	141599550	0	0
T1	31351	20568	0	0
T2	8881	0	0	0
T3	8464	0	0	0
T4	519576	512672	0	0
T5	140222	134278	0	0
T10	7354	0	0	0
T11	9582	0	0	0
T12	9232	576	0	0
T13	7298	568	0	0
T14	96386	0	0	0
T15	0	567	0	0
T18	0	563	0	0
T81	0	111361	0	0
T83	0	2696	0	0
T84	0	5478	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	141599550	0	0
T1	31351	20568	0	0
T2	8881	0	0	0
T3	8464	0	0	0
T4	519576	512672	0	0
T5	140222	134278	0	0
T10	7354	0	0	0
T11	9582	0	0	0
T12	9232	576	0	0
T13	7298	568	0	0
T14	96386	0	0	0
T15	0	567	0	0
T18	0	563	0	0
T81	0	111361	0	0
T83	0	2696	0	0
T84	0	5478	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	14	9	64.29
Logical	14	9	64.29
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T83
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T4

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375709729	282512626	0	0
DepthKnown_A	375709729	375490852	0	0
RvalidKnown_A	375709729	375490852	0	0
WreadyKnown_A	375709729	375490852	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	375709729	282512626	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	282512626	0	0
T1	31351	21178	0	0
T2	8881	310	0	0
T3	8464	1036	0	0
T4	519576	512656	0	0
T5	140222	134262	0	0
T10	7354	705	0	0
T11	9582	1202	0	0
T12	9232	0	0	0
T13	7298	0	0	0
T14	96386	0	0	0
T16	0	238060	0	0
T17	0	27928	0	0
T83	0	2820	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	282512626	0	0
T1	31351	21178	0	0
T2	8881	310	0	0
T3	8464	1036	0	0
T4	519576	512656	0	0
T5	140222	134262	0	0
T10	7354	705	0	0
T11	9582	1202	0	0
T12	9232	0	0	0
T13	7298	0	0	0
T14	96386	0	0	0
T16	0	238060	0	0
T17	0	27928	0	0
T83	0	2820	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T37,T38
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T2,T10,T4

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T2,T10,T4

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T2,T10,T4
1	1	0	Not Covered
1	1	1	Covered	T10,T4,T11

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T2,T10,T4
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T2,T10,T4

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375709729	49496136	0	0
DepthKnown_A	375709729	375490852	0	0
RvalidKnown_A	375709729	375490852	0	0
WreadyKnown_A	375709729	375490852	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	375709729	49496136	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	49496136	0	0
T2	8881	1241	0	0
T3	8464	0	0	0
T4	519576	423	0	0
T5	140222	371	0	0
T10	7354	91	0	0
T11	9582	110	0	0
T12	9232	843	0	0
T13	7298	902	0	0
T14	96386	0	0	0
T15	8362	111	0	0
T16	0	16897	0	0
T17	0	1099	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	49496136	0	0
T2	8881	1241	0	0
T3	8464	0	0	0
T4	519576	423	0	0
T5	140222	371	0	0
T10	7354	91	0	0
T11	9582	110	0	0
T12	9232	843	0	0
T13	7298	902	0	0
T14	96386	0	0	0
T15	8362	111	0	0
T16	0	16897	0	0
T17	0	1099	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	377396895	18850726	0	0
DepthKnown_A	377396895	377138131	0	0
RvalidKnown_A	377396895	377138131	0	0
WreadyKnown_A	377396895	377138131	0	0
gen_passthru_fifo.paramCheckPass	3014	3014	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	18850726	0	0
T1	31351	60	0	0
T2	8881	12	0	0
T3	8464	10	0	0
T4	519576	169652	0	0
T5	140222	66760	0	0
T10	7354	15	0	0
T11	9582	15	0	0
T12	9232	13	0	0
T13	7298	9	0	0
T14	96386	40152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3014	3014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	377396895	26672992	0	0
DepthKnown_A	377396895	377138131	0	0
RvalidKnown_A	377396895	377138131	0	0
WreadyKnown_A	377396895	377138131	0	0
gen_passthru_fifo.paramCheckPass	3014	3014	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	26672992	0	0
T1	31351	60	0	0
T2	8881	51	0	0
T3	8464	10	0	0
T4	519576	169652	0	0
T5	140222	66760	0	0
T10	7354	15	0	0
T11	9582	15	0	0
T12	9232	13	0	0
T13	7298	9	0	0
T14	96386	40152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3014	3014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	377396895	849667	0	0
DepthKnown_A	377396895	377138131	0	0
RvalidKnown_A	377396895	377138131	0	0
WreadyKnown_A	377396895	377138131	0	0
gen_passthru_fifo.paramCheckPass	3014	3014	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	849667	0	0
T1	31351	6	0	0
T2	8881	0	0	0
T3	8464	0	0	0
T4	519576	0	0	0
T5	140222	0	0	0
T10	7354	3	0	0
T11	9582	0	0	0
T12	9232	0	0	0
T13	7298	0	0	0
T14	96386	0	0	0
T15	0	2	0	0
T16	0	3896	0	0
T17	0	101	0	0
T18	0	30	0	0
T19	0	61	0	0
T50	0	4409	0	0
T70	0	16480	0	0
T85	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3014	3014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	377396895	1575302	0	0
DepthKnown_A	377396895	377138131	0	0
RvalidKnown_A	377396895	377138131	0	0
WreadyKnown_A	377396895	377138131	0	0
gen_passthru_fifo.paramCheckPass	3014	3014	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	1575302	0	0
T1	31351	6	0	0
T2	8881	0	0	0
T3	8464	0	0	0
T4	519576	0	0	0
T5	140222	0	0	0
T10	7354	3	0	0
T11	9582	0	0	0
T12	9232	0	0	0
T13	7298	0	0	0
T14	96386	0	0	0
T15	0	13	0	0
T16	0	3896	0	0
T17	0	101	0	0
T18	0	30	0	0
T19	0	61	0	0
T50	0	19837	0	0
T70	0	74542	0	0
T85	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3014	3014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	377396895	17943430	0	0
DepthKnown_A	377396895	377138131	0	0
RvalidKnown_A	377396895	377138131	0	0
WreadyKnown_A	377396895	377138131	0	0
gen_passthru_fifo.paramCheckPass	3014	3014	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	17943430	0	0
T1	31351	54	0	0
T2	8881	12	0	0
T3	8464	10	0	0
T4	519576	169652	0	0
T5	140222	66760	0	0
T10	7354	12	0	0
T11	9582	15	0	0
T12	9232	13	0	0
T13	7298	9	0	0
T14	96386	40152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3014	3014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	377396895	25097690	0	0
DepthKnown_A	377396895	377138131	0	0
RvalidKnown_A	377396895	377138131	0	0
WreadyKnown_A	377396895	377138131	0	0
gen_passthru_fifo.paramCheckPass	3014	3014	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	25097690	0	0
T1	31351	54	0	0
T2	8881	51	0	0
T3	8464	10	0	0
T4	519576	169652	0	0
T5	140222	66760	0	0
T10	7354	12	0	0
T11	9582	15	0	0
T12	9232	13	0	0
T13	7298	9	0	0
T14	96386	40152	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	377396895	377138131	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3014	3014	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T15
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T10,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T15,T16
1	1	0	Not Covered
1	1	1	Covered	T1,T10,T15

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T10,T15
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T10,T15

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T10,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375709729	1531990	0	0
DepthKnown_A	375709729	375490852	0	0
RvalidKnown_A	375709729	375490852	0	0
WreadyKnown_A	375709729	375490852	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	375709729	1531990	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	1531990	0	0
T1	31351	6	0	0
T2	8881	0	0	0
T3	8464	0	0	0
T4	519576	0	0	0
T5	140222	0	0	0
T10	7354	3	0	0
T11	9582	0	0	0
T12	9232	0	0	0
T13	7298	0	0	0
T14	96386	0	0	0
T15	0	13	0	0
T16	0	3896	0	0
T17	0	101	0	0
T18	0	30	0	0
T19	0	61	0	0
T50	0	19837	0	0
T70	0	74542	0	0
T85	0	2	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	1531990	0	0
T1	31351	6	0	0
T2	8881	0	0	0
T3	8464	0	0	0
T4	519576	0	0	0
T5	140222	0	0	0
T10	7354	3	0	0
T11	9582	0	0	0
T12	9232	0	0	0
T13	7298	0	0	0
T14	96386	0	0	0
T15	0	13	0	0
T16	0	3896	0	0
T17	0	101	0	0
T18	0	30	0	0
T19	0	61	0	0
T50	0	19837	0	0
T70	0	74542	0	0
T85	0	2	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	10	62.50
Logical	16	10	62.50
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T15,T16
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T15,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T15,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T15,T16

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T10,T15,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T10,T15,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375709729	556061	0	0
DepthKnown_A	375709729	375490852	0	0
RvalidKnown_A	375709729	375490852	0	0
WreadyKnown_A	375709729	375490852	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	375709729	556061	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	556061	0	0
T4	519576	0	0	0
T5	140222	0	0	0
T10	7354	3	0	0
T11	9582	0	0	0
T12	9232	0	0	0
T13	7298	0	0	0
T14	96386	0	0	0
T15	8362	2	0	0
T16	412782	2226	0	0
T17	63529	101	0	0
T18	0	17	0	0
T19	0	61	0	0
T50	0	2616	0	0
T70	0	16480	0	0
T85	0	2	0	0
T86	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	556061	0	0
T4	519576	0	0	0
T5	140222	0	0	0
T10	7354	3	0	0
T11	9582	0	0	0
T12	9232	0	0	0
T13	7298	0	0	0
T14	96386	0	0	0
T15	8362	2	0	0
T16	412782	2226	0	0
T17	63529	101	0	0
T18	0	17	0	0
T19	0	61	0	0
T50	0	2616	0	0
T70	0	16480	0	0
T85	0	2	0	0
T86	0	16	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	24	18	75.00
Logical	24	18	75.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T50,T70
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T10,T15,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T10,T15,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T15,T16,T17
1	1	0	Not Covered
1	1	1	Covered	T10,T15,T16

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T10,T15,T16

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T10,T15,T16

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T15,T50,T70
1	0	Covered	T10,T15,T16
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T10,T15,T16
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T15,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T10,T15,T16

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T10,T15,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	375709729	1084246	0	0
DepthKnown_A	375709729	375490852	0	0
RvalidKnown_A	375709729	375490852	0	0
WreadyKnown_A	375709729	375490852	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	375709729	1084246	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	1084246	0	0
T4	519576	0	0	0
T5	140222	0	0	0
T10	7354	3	0	0
T11	9582	0	0	0
T12	9232	0	0	0
T13	7298	0	0	0
T14	96386	0	0	0
T15	8362	13	0	0
T16	412782	2226	0	0
T17	63529	101	0	0
T18	0	17	0	0
T19	0	61	0	0
T50	0	11737	0	0
T70	0	74542	0	0
T85	0	2	0	0
T86	0	82	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	375490852	0	0
T1	31351	31285	0	0
T2	8881	8794	0	0
T3	8464	8380	0	0
T4	519576	519482	0	0
T5	140222	140131	0	0
T10	7354	7264	0	0
T11	9582	9482	0	0
T12	9232	9162	0	0
T13	7298	7220	0	0
T14	96386	96286	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	375709729	1084246	0	0
T4	519576	0	0	0
T5	140222	0	0	0
T10	7354	3	0	0
T11	9582	0	0	0
T12	9232	0	0	0
T13	7298	0	0	0
T14	96386	0	0	0
T15	8362	13	0	0
T16	412782	2226	0	0
T17	63529	101	0	0
T18	0	17	0	0
T19	0	61	0	0
T50	0	11737	0	0
T70	0	74542	0	0
T85	0	2	0	0
T86	0	82	0	0