Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	61190	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	60415	1		T1	378		T2	28		T3	1462

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	74757	1		T1	116		T2	20		T3	1446
values[0x0]	22974	1		T1	185		T2	10		T3	721
values[0x1]	23874	1		T1	176		T2	10		T3	724

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42123	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	79482	1		T1	439		T2	31		T3	1761

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	524	1		T3	17		T4	4		T6	8
valid_sources[0x01]	422	1		T1	6		T3	12		T5	3
valid_sources[0x02]	301	1		T1	7		T3	17		T5	9
valid_sources[0x03]	338	1		T1	2		T3	8		T8	8
valid_sources[0x04]	614	1		T3	9		T5	16		T6	2
valid_sources[0x05]	278	1		T1	1		T3	3		T4	4
valid_sources[0x06]	493	1		T3	9		T5	27		T6	6
valid_sources[0x07]	330	1		T3	9		T6	4		T7	1
valid_sources[0x08]	385	1		T3	10		T5	17		T6	1
valid_sources[0x09]	385	1		T3	16		T4	5		T5	18
valid_sources[0x0a]	453	1		T1	1		T3	3		T6	4
valid_sources[0x0b]	601	1		T1	1		T3	21		T5	21
valid_sources[0x0c]	659	1		T1	3		T3	19		T4	2
valid_sources[0x0d]	578	1		T1	2		T3	7		T5	22
valid_sources[0x0e]	526	1		T1	4		T3	8		T14	1
valid_sources[0x0f]	370	1		T1	2		T3	15		T5	1
valid_sources[0x10]	473	1		T1	3		T3	6		T14	1
valid_sources[0x11]	412	1		T1	4		T3	15		T4	18
valid_sources[0x12]	406	1		T1	5		T3	3		T5	4
valid_sources[0x13]	407	1		T1	2		T3	13		T14	1
valid_sources[0x14]	324	1		T1	2		T3	9		T5	19
valid_sources[0x15]	328	1		T1	1		T3	1		T6	6
valid_sources[0x16]	356	1		T1	4		T3	3		T5	2
valid_sources[0x17]	391	1		T3	10		T6	7		T17	7
valid_sources[0x18]	497	1		T3	22		T6	4		T7	1
valid_sources[0x19]	419	1		T1	3		T3	27		T6	5
valid_sources[0x1a]	3534	1		T1	2		T3	4		T5	2
valid_sources[0x1b]	334	1		T1	1		T3	20		T4	14
valid_sources[0x1c]	305	1		T1	3		T3	8		T5	3
valid_sources[0x1d]	310	1		T1	1		T3	12		T5	4
valid_sources[0x1e]	385	1		T1	4		T3	3		T8	3
valid_sources[0x1f]	578	1		T1	8		T3	7		T6	3
valid_sources[0x20]	380	1		T1	2		T3	8		T8	3
valid_sources[0x21]	386	1		T1	2		T5	9		T6	7
valid_sources[0x22]	474	1		T3	12		T4	2		T5	6
valid_sources[0x23]	514	1		T1	1		T3	8		T5	9
valid_sources[0x24]	328	1		T1	1		T3	12		T4	4
valid_sources[0x25]	591	1		T3	16		T5	3		T6	3
valid_sources[0x26]	418	1		T1	1		T3	7		T4	33
valid_sources[0x27]	618	1		T1	4		T3	15		T14	1
valid_sources[0x28]	329	1		T3	5		T5	1		T6	5
valid_sources[0x29]	612	1		T1	3		T3	28		T8	2
valid_sources[0x2a]	431	1		T1	2		T3	22		T5	17
valid_sources[0x2b]	645	1		T1	1		T3	12		T6	7
valid_sources[0x2c]	349	1		T1	2		T3	2		T5	29
valid_sources[0x2d]	296	1		T1	2		T3	18		T4	5
valid_sources[0x2e]	627	1		T1	1		T3	27		T5	12
valid_sources[0x2f]	477	1		T1	3		T3	6		T4	12
valid_sources[0x30]	514	1		T1	3		T3	4		T5	15
valid_sources[0x31]	365	1		T1	4		T3	8		T4	1
valid_sources[0x32]	323	1		T3	14		T5	1		T6	5
valid_sources[0x33]	369	1		T3	3		T5	7		T6	6
valid_sources[0x34]	689	1		T3	27		T5	2		T6	2
valid_sources[0x35]	461	1		T1	1		T3	23		T4	8
valid_sources[0x36]	564	1		T3	5		T4	1		T5	8
valid_sources[0x37]	408	1		T3	3		T5	4		T6	5
valid_sources[0x38]	722	1		T1	1		T3	6		T6	4
valid_sources[0x39]	479	1		T1	2		T3	6		T5	1
valid_sources[0x3a]	363	1		T1	1		T3	3		T5	6
valid_sources[0x3b]	411	1		T1	1		T3	21		T5	17
valid_sources[0x3c]	435	1		T1	2		T3	17		T5	3
valid_sources[0x3d]	373	1		T3	11		T6	4		T17	3
valid_sources[0x3e]	436	1		T1	1		T3	5		T6	10
valid_sources[0x3f]	366	1		T3	6		T5	13		T6	5
valid_sources[0x40]	394	1		T1	2		T3	16		T4	9
valid_sources[0x41]	424	1		T1	1		T3	7		T5	15
valid_sources[0x42]	759	1		T1	1		T14	1		T5	3
valid_sources[0x43]	802	1		T1	2		T3	9		T5	3
valid_sources[0x44]	514	1		T1	2		T3	4		T5	1
valid_sources[0x45]	411	1		T1	1		T3	4		T5	15
valid_sources[0x46]	2224	1		T1	3		T3	15		T6	4
valid_sources[0x47]	524	1		T4	6		T5	7		T6	8
valid_sources[0x48]	308	1		T1	2		T3	14		T14	2
valid_sources[0x49]	496	1		T1	2		T3	15		T5	11
valid_sources[0x4a]	517	1		T1	4		T3	3		T6	6
valid_sources[0x4b]	361	1		T1	7		T3	6		T5	10
valid_sources[0x4c]	360	1		T1	2		T3	6		T6	3
valid_sources[0x4d]	535	1		T1	2		T3	11		T6	4
valid_sources[0x4e]	413	1		T1	1		T3	8		T5	2
valid_sources[0x4f]	315	1		T3	8		T5	2		T6	3
valid_sources[0x50]	372	1		T1	1		T3	7		T4	13
valid_sources[0x51]	680	1		T1	1		T3	16		T6	5
valid_sources[0x52]	262	1		T1	3		T3	14		T8	1
valid_sources[0x53]	594	1		T1	2		T3	9		T5	1
valid_sources[0x54]	500	1		T1	7		T3	13		T5	15
valid_sources[0x55]	566	1		T1	1		T3	9		T5	2
valid_sources[0x56]	508	1		T1	4		T3	18		T5	4
valid_sources[0x57]	550	1		T1	3		T2	40		T3	14
valid_sources[0x58]	483	1		T3	4		T6	8		T17	6
valid_sources[0x59]	483	1		T1	6		T3	21		T14	1
valid_sources[0x5a]	531	1		T1	2		T3	18		T14	2
valid_sources[0x5b]	322	1		T1	4		T3	1		T4	5
valid_sources[0x5c]	447	1		T1	2		T3	6		T5	5
valid_sources[0x5d]	251	1		T1	1		T3	17		T4	1
valid_sources[0x5e]	754	1		T1	1		T3	17		T4	13
valid_sources[0x5f]	339	1		T1	3		T3	17		T5	4
valid_sources[0x60]	382	1		T1	1		T3	8		T4	5
valid_sources[0x61]	639	1		T1	1		T3	16		T6	8
valid_sources[0x62]	367	1		T1	3		T3	10		T5	2
valid_sources[0x63]	426	1		T3	12		T5	14		T6	3
valid_sources[0x64]	342	1		T3	13		T5	2		T6	5
valid_sources[0x65]	565	1		T1	6		T3	4		T4	20
valid_sources[0x66]	266	1		T1	5		T3	30		T5	6
valid_sources[0x67]	473	1		T3	4		T8	22		T14	1
valid_sources[0x68]	425	1		T1	1		T3	24		T6	6
valid_sources[0x69]	309	1		T1	1		T3	12		T4	3
valid_sources[0x6a]	378	1		T1	2		T3	6		T5	7
valid_sources[0x6b]	408	1		T1	3		T3	20		T5	10
valid_sources[0x6c]	395	1		T1	2		T3	13		T4	3
valid_sources[0x6d]	561	1		T1	1		T3	20		T4	4
valid_sources[0x6e]	499	1		T1	5		T3	7		T5	5
valid_sources[0x6f]	344	1		T3	18		T5	4		T6	1
valid_sources[0x70]	874	1		T3	8		T4	4		T5	3
valid_sources[0x71]	486	1		T1	1		T3	5		T6	3
valid_sources[0x72]	301	1		T1	1		T3	4		T4	8
valid_sources[0x73]	456	1		T3	10		T4	11		T5	4
valid_sources[0x74]	354	1		T3	7		T5	2		T6	8
valid_sources[0x75]	340	1		T1	2		T3	4		T5	6
valid_sources[0x76]	530	1		T1	2		T3	1		T5	4
valid_sources[0x77]	652	1		T1	1		T3	4		T8	17
valid_sources[0x78]	547	1		T1	2		T3	9		T5	3
valid_sources[0x79]	576	1		T1	3		T3	7		T6	8
valid_sources[0x7a]	383	1		T1	2		T3	12		T6	9
valid_sources[0x7b]	805	1		T3	10		T6	6		T17	1
valid_sources[0x7c]	580	1		T3	1		T4	11		T5	13
valid_sources[0x7d]	557	1		T1	1		T3	14		T4	12
valid_sources[0x7e]	746	1		T1	1		T3	5		T4	1
valid_sources[0x7f]	478	1		T1	1		T3	2		T6	6
valid_sources[0x80]	315	1		T3	7		T4	6		T5	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23591

1

T1

17

T2

10

T3

686

values[0x0]

all_enables

biggest_size

19591

1

T1

185

T2

10

T3

479

values[0x1]

all_enables

biggest_size

17233

1

T1

176

T2

8

T3

297