Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	75541	1		T1	99		T2	12		T3	1429
full_word	61290	1		T1	378		T2	28		T3	1462

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	136511	1		T1	477		T2	40		T3	2891
auto[TlIntgErrCmd]	113	1		T5	3		T6	5		T9	4
auto[TlIntgErrData]	105	1		T5	3		T6	2		T9	4
auto[TlIntgErrBoth]	102	1		T5	4		T6	3		T9	2

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	76477	1		T1	116		T2	20		T3	1446
auto[1]	60354	1		T1	361		T2	20		T3	1445

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	52586	1		T1	99		T2	10		T3	760
auto[TlIntgErrNone]	partial	auto[1]	22661	1		T2	2		T3	669		T8	8
auto[TlIntgErrNone]	full_word	auto[0]	23746	1		T1	17		T2	10		T3	686
auto[TlIntgErrNone]	full_word	auto[1]	37518	1		T1	361		T2	18		T3	776
auto[TlIntgErrCmd]	partial	auto[0]	48	1		T6	1		T9	2		T27	3
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T5	2		T6	2		T9	2
auto[TlIntgErrCmd]	full_word	auto[0]	6	1		T5	1		T28	2		T80	1
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T6	2		T31	1		T81	1
auto[TlIntgErrData]	partial	auto[0]	42	1		T5	1		T6	1		T9	1
auto[TlIntgErrData]	partial	auto[1]	54	1		T5	2		T9	2		T27	2
auto[TlIntgErrData]	full_word	auto[0]	5	1		T29	1		T30	1		T31	1
auto[TlIntgErrData]	full_word	auto[1]	4	1		T6	1		T9	1		T79	1
auto[TlIntgErrBoth]	partial	auto[0]	41	1		T5	2		T27	3		T28	4
auto[TlIntgErrBoth]	partial	auto[1]	56	1		T5	2		T6	3		T9	2
auto[TlIntgErrBoth]	full_word	auto[0]	3	1		T82	1		T78	1		T83	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T28	1		T79	1		-	-