Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
22.73	0.00	0.00	90.91		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1760731	11755	0	0
ep_in_enable_rd_A	1760731	3079	0	0
ep_out_enable_rd_A	1760731	3004	0	0
in_iso_rd_A	1760731	3552	0	0
intr_enable_rd_A	1760731	4818	0	0
out_iso_rd_A	1760731	2970	0	0
phy_config_rd_A	1760731	2200	0	0
phy_pins_drive_rd_A	1760731	2491	0	0
rxenable_setup_rd_A	1760731	3127	0	0
set_nak_out_rd_A	1760731	3491	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1760731	11755	0	0
T5	24702	3	0	0
T6	21791	3	0	0
T7	4189	0	0	0
T9	30419	3	0	0
T15	1876	0	0	0
T16	1840	0	0	0
T17	3437	0	0	0
T18	0	24	0	0
T19	0	366	0	0
T21	0	18	0	0
T22	0	11	0	0
T27	59222	5	0	0
T28	0	4	0	0
T29	0	4	0	0
T32	6823	0	0	0
T33	7438	0	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1760731	3079	0	0
T5	24702	274	0	0
T6	21791	0	0	0
T7	4189	0	0	0
T9	30419	205	0	0
T15	1876	0	0	0
T16	1840	0	0	0
T17	3437	0	0	0
T27	59222	0	0	0
T29	0	449	0	0
T30	0	571	0	0
T32	6823	0	0	0
T33	7438	0	0	0
T35	0	9	0	0
T65	0	16	0	0
T66	0	73	0	0
T67	0	5	0	0
T68	0	29	0	0
T69	0	6	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1760731	3004	0	0
T5	24702	156	0	0
T6	21791	0	0	0
T7	4189	0	0	0
T9	30419	245	0	0
T15	1876	0	0	0
T16	1840	0	0	0
T17	3437	0	0	0
T27	59222	0	0	0
T29	0	479	0	0
T30	0	447	0	0
T32	6823	0	0	0
T33	7438	0	0	0
T35	0	22	0	0
T65	0	57	0	0
T66	0	80	0	0
T67	0	12	0	0
T68	0	19	0	0
T70	0	12	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1760731	3552	0	0
T5	24702	212	0	0
T6	21791	0	0	0
T7	4189	0	0	0
T9	30419	293	0	0
T15	1876	0	0	0
T16	1840	0	0	0
T17	3437	0	0	0
T27	59222	0	0	0
T29	0	600	0	0
T30	0	646	0	0
T32	6823	0	0	0
T33	7438	0	0	0
T35	0	11	0	0
T65	0	42	0	0
T66	0	14	0	0
T67	0	1	0	0
T68	0	44	0	0
T70	0	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1760731	4818	0	0
T5	24702	524	0	0
T6	21791	0	0	0
T7	4189	8	0	0
T9	30419	426	0	0
T15	1876	19	0	0
T16	1840	0	0	0
T17	3437	0	0	0
T27	59222	0	0	0
T29	0	779	0	0
T32	6823	0	0	0
T33	7438	0	0	0
T35	0	13	0	0
T36	0	10	0	0
T41	0	25	0	0
T71	0	5	0	0
T72	0	6	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1760731	2970	0	0
T5	24702	198	0	0
T6	21791	0	0	0
T7	4189	0	0	0
T9	30419	206	0	0
T15	1876	0	0	0
T16	1840	0	0	0
T17	3437	0	0	0
T27	59222	0	0	0
T29	0	388	0	0
T30	0	451	0	0
T32	6823	0	0	0
T33	7438	0	0	0
T35	0	42	0	0
T65	0	47	0	0
T66	0	14	0	0
T67	0	1	0	0
T68	0	1	0	0
T70	0	9	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1760731	2200	0	0
T5	24702	208	0	0
T6	21791	0	0	0
T7	4189	0	0	0
T9	30419	165	0	0
T15	1876	0	0	0
T16	1840	0	0	0
T17	3437	0	0	0
T27	59222	0	0	0
T29	0	178	0	0
T30	0	297	0	0
T32	6823	0	0	0
T33	7438	0	0	0
T35	0	18	0	0
T65	0	90	0	0
T66	0	18	0	0
T67	0	9	0	0
T68	0	54	0	0
T70	0	6	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1760731	2491	0	0
T5	24702	216	0	0
T6	21791	0	0	0
T7	4189	0	0	0
T9	30419	197	0	0
T15	1876	0	0	0
T16	1840	0	0	0
T17	3437	0	0	0
T27	59222	0	0	0
T29	0	271	0	0
T30	0	286	0	0
T32	6823	0	0	0
T33	7438	0	0	0
T35	0	7	0	0
T65	0	21	0	0
T66	0	28	0	0
T67	0	5	0	0
T68	0	13	0	0
T70	0	8	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1760731	3127	0	0
T5	24702	291	0	0
T6	21791	0	0	0
T7	4189	0	0	0
T9	30419	229	0	0
T15	1876	0	0	0
T16	1840	0	0	0
T17	3437	0	0	0
T27	59222	0	0	0
T29	0	619	0	0
T30	0	379	0	0
T32	6823	0	0	0
T33	7438	0	0	0
T35	0	31	0	0
T65	0	34	0	0
T66	0	57	0	0
T67	0	25	0	0
T68	0	5	0	0
T69	0	61	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1760731	3491	0	0
T5	24702	238	0	0
T6	21791	0	0	0
T7	4189	0	0	0
T9	30419	252	0	0
T15	1876	0	0	0
T16	1840	0	0	0
T17	3437	0	0	0
T27	59222	0	0	0
T29	0	619	0	0
T30	0	558	0	0
T32	6823	0	0	0
T33	7438	0	0	0
T35	0	24	0	0
T65	0	23	0	0
T66	0	42	0	0
T68	0	11	0	0
T69	0	2	0	0
T70	0	1	0	0