c8985d6745| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | usbdev_smoke | 0 | 50 | 0.00 | ||
| V1 | csr_hw_reset | usbdev_csr_hw_reset | 0.980s | 111.112us | 5 | 5 | 100.00 |
| V1 | csr_rw | usbdev_csr_rw | 1.070s | 98.202us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | usbdev_csr_bit_bash | 8.450s | 1.350ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | usbdev_csr_aliasing | 3.760s | 302.651us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | usbdev_csr_mem_rw_with_rand_reset | 2.380s | 88.080us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | usbdev_csr_rw | 1.070s | 98.202us | 20 | 20 | 100.00 |
| usbdev_csr_aliasing | 3.760s | 302.651us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | usbdev_mem_walk | 4.640s | 775.262us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | usbdev_mem_partial_access | 2.360s | 166.535us | 5 | 5 | 100.00 |
| V1 | TOTAL | 65 | 115 | 56.52 | |||
| V2 | in_trans | usbdev_in_trans | 0 | 50 | 0.00 | ||
| V2 | data_toggle_clear | usbdev_data_toggle_clear | 0 | 50 | 0.00 | ||
| V2 | phy_pins_sense | usbdev_phy_pins_sense | 0 | 50 | 0.00 | ||
| V2 | av_buffer | usbdev_av_buffer | 0 | 50 | 0.00 | ||
| V2 | rx_fifo | usbdev_pkt_buffer | 0 | 50 | 0.00 | ||
| V2 | phy_config_tx_osc_test_mode | usbdev_phy_config_tx_osc_test_mode | 0 | 1 | 0.00 | ||
| V2 | phy_config_eop_single_bit_handling | usbdev_phy_config_eop_single_bit_handling | 0 | 1 | 0.00 | ||
| V2 | phy_config_pinflip | usbdev_phy_config_pinflip | 0 | 50 | 0.00 | ||
| V2 | phy_config_rand_bus_type | usbdev_phy_config_rand_bus_type | 0 | 5 | 0.00 | ||
| V2 | phy_config_rx_dp_dn | usbdev_phy_config_rx_dp_dn | 0 | 1 | 0.00 | ||
| V2 | phy_config_tx_use_d_se0 | usbdev_phy_config_tx_use_d_se0 | 0 | 1 | 0.00 | ||
| V2 | phy_config_usb_ref_disable | usbdev_phy_config_usb_ref_disable | 0 | 50 | 0.00 | ||
| V2 | max_length_out_transaction | usbdev_max_length_out_transaction | 0 | 50 | 0.00 | ||
| usbdev_stream_len_max | 0 | 50 | 0.00 | ||||
| V2 | max_length_in_transaction | usbdev_max_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | min_length_out_transaction | usbdev_min_length_out_transaction | 0 | 50 | 0.00 | ||
| V2 | min_length_in_transaction | usbdev_min_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | random_length_out_transaction | usbdev_random_length_out_transaction | 0 | 50 | 0.00 | ||
| V2 | random_length_in_transaction | usbdev_random_length_in_transaction | 0 | 50 | 0.00 | ||
| V2 | out_stall | usbdev_out_stall | 0 | 50 | 0.00 | ||
| V2 | in_stall | usbdev_in_stall | 0 | 50 | 0.00 | ||
| V2 | out_iso | usbdev_out_iso | 0 | 50 | 0.00 | ||
| V2 | in_iso | usbdev_in_iso | 0 | 50 | 0.00 | ||
| V2 | pkt_received | usbdev_pkt_received | 0 | 50 | 0.00 | ||
| V2 | pkt_sent | usbdev_pkt_sent | 0 | 50 | 0.00 | ||
| V2 | disconnected | usbdev_disconnected | 0 | 50 | 0.00 | ||
| V2 | host_lost | usbdev_host_lost | 0 | 1 | 0.00 | ||
| V2 | link_reset | usbdev_link_reset | 0 | 1 | 0.00 | ||
| V2 | link_suspend | usbdev_link_suspend | 0 | 50 | 0.00 | ||
| V2 | link_resume | usbdev_link_resume | 0 | 50 | 0.00 | ||
| V2 | av_empty | usbdev_av_empty | 0 | 5 | 0.00 | ||
| V2 | rx_full | usbdev_rx_full | 0 | 50 | 0.00 | ||
| V2 | av_overflow | usbdev_av_overflow | 0 | 5 | 0.00 | ||
| V2 | link_in_err | usbdev_link_in_err | 0 | 50 | 0.00 | ||
| V2 | rx_crc_err | usbdev_rx_crc_err | 0 | 50 | 0.00 | ||
| V2 | rx_pid_err | usbdev_rx_pid_err | 0 | 5 | 0.00 | ||
| V2 | rx_bitstuff_err | usbdev_bitstuff_err | 0 | 50 | 0.00 | ||
| V2 | link_out_err | usbdev_link_out_err | 0 | 1 | 0.00 | ||
| V2 | enable | usbdev_enable | 0 | 50 | 0.00 | ||
| V2 | resume_link_active | usbdev_resume_link_active | 0 | 1 | 0.00 | ||
| V2 | device_address | usbdev_device_address | 0 | 50 | 0.00 | ||
| V2 | invalid_data1_data0_toggle_test | usbdev_invalid_data1_data0_toggle_test | 0 | 1 | 0.00 | ||
| V2 | setup_stage | usbdev_setup_stage | 0 | 50 | 0.00 | ||
| V2 | endpoint_access | usbdev_endpoint_access | 0 | 50 | 0.00 | ||
| V2 | disable_endpoint | usbdev_disable_endpoint | 0 | 50 | 0.00 | ||
| V2 | endpoint_types | usbdev_endpoint_types | 0 | 200 | 0.00 | ||
| V2 | out_trans_nak | usbdev_out_trans_nak | 0 | 50 | 0.00 | ||
| V2 | setup_trans_ignored | usbdev_setup_trans_ignored | 0 | 50 | 0.00 | ||
| V2 | nak_trans | usbdev_nak_trans | 0 | 50 | 0.00 | ||
| V2 | stall_trans | usbdev_stall_trans | 0 | 50 | 0.00 | ||
| V2 | setup_priority_over_stall_response | usbdev_setup_priority_over_stall_response | 0 | 5 | 0.00 | ||
| V2 | stall_priority_over_nak | usbdev_stall_priority_over_nak | 0 | 50 | 0.00 | ||
| V2 | pending_in_trans | usbdev_pending_in_trans | 0 | 50 | 0.00 | ||
| V2 | streaming_test | usbdev_streaming_out | 0 | 50 | 0.00 | ||
| V2 | max_clock_error_untracked | usbdev_freq_hiclk | 0 | 5 | 0.00 | ||
| usbdev_freq_loclk | 0 | 5 | 0.00 | ||||
| V2 | max_clock_error_tracking | usbdev_freq_hiclk_max | 0 | 5 | 0.00 | ||
| usbdev_freq_loclk_max | 0 | 5 | 0.00 | ||||
| V2 | max_phase_error | usbdev_freq_phase | 0 | 5 | 0.00 | ||
| V2 | min_inter_pkt_delay | usbdev_min_inter_pkt_delay | 0 | 50 | 0.00 | ||
| V2 | max_inter_pkt_delay | usbdev_max_inter_pkt_delay | 0 | 50 | 0.00 | ||
| V2 | device_timeout_missing_host_handshake | usbdev_timeout_missing_host_handshake | 0 | 50 | 0.00 | ||
| V2 | device_timeout | usbdev_device_timeout | 0 | 50 | 0.00 | ||
| V2 | packet_buffer | usbdev_pkt_buffer | 0 | 50 | 0.00 | ||
| V2 | nak_to_out_trans_when_avbuffer_empty_rxfifo_full | usbdev_nak_to_out_trans_when_avbuffer_empty_rxfifo_full | 0 | 1 | 0.00 | ||
| V2 | aon_wake_resume | usbdev_aon_wake_resume | 0 | 50 | 0.00 | ||
| V2 | aon_wake_reset | usbdev_aon_wake_reset | 0 | 50 | 0.00 | ||
| V2 | aon_wake_disconnect | usbdev_aon_wake_disconnect | 0 | 50 | 0.00 | ||
| V2 | invalid_sync | usbdev_invalid_sync | 0 | 50 | 0.00 | ||
| V2 | spurious_pids_ignored | usbdev_spurious_pids_ignored | 0 | 50 | 0.00 | ||
| V2 | low_speed_traffic | usbdev_low_speed_traffic | 0 | 50 | 0.00 | ||
| V2 | rand_bus_resets | usbdev_rand_bus_resets | 0 | 10 | 0.00 | ||
| V2 | rand_disconnects | usbdev_rand_bus_disconnects | 0 | 10 | 0.00 | ||
| V2 | rand_suspends | usbdev_rand_suspends | 0 | 10 | 0.00 | ||
| V2 | max_usb_traffic | usbdev_max_non_iso_usb_traffic | 0 | 25 | 0.00 | ||
| usbdev_max_usb_traffic | 0 | 15 | 0.00 | ||||
| V2 | stress_usb_traffic | usbdev_stress_usb_traffic | 0 | 5 | 0.00 | ||
| V2 | in_packet_retraction | usbdev_iso_retraction | 0 | 50 | 0.00 | ||
| V2 | data_toggle_restore | usbdev_data_toggle_restore | 0 | 50 | 0.00 | ||
| V2 | setup_priority | usbdev_setup_priority | 0 | 5 | 0.00 | ||
| V2 | fifo_resets | usbdev_fifo_rst | 0 | 50 | 0.00 | ||
| V2 | intr_test | usbdev_intr_test | 0.850s | 114.109us | 50 | 50 | 100.00 |
| V2 | alert_test | usbdev_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | usbdev_tl_errors | 3.780s | 132.068us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | usbdev_tl_errors | 3.780s | 132.068us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | usbdev_csr_hw_reset | 0.980s | 111.112us | 5 | 5 | 100.00 |
| usbdev_csr_rw | 1.070s | 98.202us | 20 | 20 | 100.00 | ||
| usbdev_csr_aliasing | 3.760s | 302.651us | 5 | 5 | 100.00 | ||
| usbdev_same_csr_outstanding | 1.840s | 144.935us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | usbdev_csr_hw_reset | 0.980s | 111.112us | 5 | 5 | 100.00 |
| usbdev_csr_rw | 1.070s | 98.202us | 20 | 20 | 100.00 | ||
| usbdev_csr_aliasing | 3.760s | 302.651us | 5 | 5 | 100.00 | ||
| usbdev_same_csr_outstanding | 1.840s | 144.935us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 90 | 3080 | 2.92 | |||
| V2S | tl_intg_err | usbdev_sec_cm | 0 | 5 | 0.00 | ||
| usbdev_tl_intg_err | 6.220s | 2.225ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | usbdev_tl_intg_err | 6.220s | 2.225ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 20 | 25 | 80.00 | |||
| V3 | dpi_config_host | usbdev_dpi_config_host | 0 | 1 | 0.00 | ||
| V3 | TOTAL | 0 | 1 | 0.00 | |||
| Unmapped tests | usbdev_stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| usbdev_stress_all | 0 | 50 | 0.00 | ||||
| TOTAL | 175 | 3281 | 5.33 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 2 | 2 | 0 | 0.00 |
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 84 | 84 | 3 | 3.57 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 60.95 | 65.68 | 59.58 | 86.57 | 0.00 | 69.84 | 97.77 | 47.24 |
launch_task.returncode != *, err: * *:*:* * lswatcher.go:*] Failed to connect to Watcher service in the Envelope (you probably need to import _ "google3/tech/env/go/envelope"): generic::unimplemented: envrpc: no envelope available for service "chubby.googleapis.com" Failure to submit jobs: rpc error: code = Unavailable desc = The service is currently unavailable. has 1553 failures:
0.usbdev_aon_wake_disconnect.35610092567006610562772535036458708971848325056426827080679822347971479379716
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_disconnect/latest/run.log
1.usbdev_aon_wake_disconnect.64152224291372216793261471052904531198037495232152754639767992975477668265814
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_aon_wake_disconnect/latest/run.log
... and 41 more failures.
0.usbdev_aon_wake_resume.104268132718552471278712544048293682468277201560724499553584277788221072775282
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_resume/latest/run.log
1.usbdev_aon_wake_resume.59510883578215806532773454522342785970970909850553942192479113189875723199193
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_aon_wake_resume/latest/run.log
... and 41 more failures.
0.usbdev_av_empty.33392188347691467259337857561905261641196723745493611256896917216976806046560
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_empty/latest/run.log
1.usbdev_av_empty.15878148335344200803016313729863450735280559516585348488755868001633114462534
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_av_empty/latest/run.log
... and 1 more failures.
0.usbdev_bitstuff_err.12148548689767287878036410879434546179272605700680777737009708973619898710238
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_bitstuff_err/latest/run.log
1.usbdev_bitstuff_err.36867742090876931887360215863930495759347972108494022470067768301023821040123
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_bitstuff_err/latest/run.log
... and 41 more failures.
0.usbdev_data_toggle_restore.7779285422182552227925018745582410232470123442077097005401284682524606452971
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_data_toggle_restore/latest/run.log
1.usbdev_data_toggle_restore.33593992015017597305711019388051682999168486362424459927423573759538194947069
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_data_toggle_restore/latest/run.log
... and 41 more failures.
Job killed most likely because its dependent job failed. has 1553 failures:
0.usbdev_aon_wake_reset.19095425761729032321899724038173239654922230207694553419640917503569912706771
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_aon_wake_reset/latest/run.log
1.usbdev_aon_wake_reset.10099304804264278701232246475365050586480571177570300235117049254826775149608
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_aon_wake_reset/latest/run.log
... and 41 more failures.
0.usbdev_av_buffer.14740124843069441571879133908361929375777619922478628915693027744486528243173
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_buffer/latest/run.log
1.usbdev_av_buffer.23232306356157650804826306127476479835980597776430896396066034396597683493180
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_av_buffer/latest/run.log
... and 41 more failures.
0.usbdev_av_overflow.54913261850820414602852706825147409870414359718406293487891226670500802199248
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_av_overflow/latest/run.log
1.usbdev_av_overflow.36613654339742346790079741207451600823216117222850984733176884389970601707338
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_av_overflow/latest/run.log
... and 1 more failures.
0.usbdev_data_toggle_clear.44376386605234180792176089230803551257915813303385084786781260030249810011987
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_data_toggle_clear/latest/run.log
1.usbdev_data_toggle_clear.14480571826037625648492242948429144775964497976879210233799591084608327771230
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_data_toggle_clear/latest/run.log
... and 41 more failures.
0.usbdev_device_address.113084453138076134303288521474638509053449952178039635186186506205750338443041
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/0.usbdev_device_address/latest/run.log
1.usbdev_device_address.110640178262368279944185013064893061137240289905964423636347239269483175738340
Log /container/opentitan-public/scratch/os_regression/usbdev-sim-vcs/1.usbdev_device_address/latest/run.log
... and 41 more failures.