Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	57600	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	61392	1		T1	44		T2	380		T3	1460

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	71876	1		T1	235		T2	390		T3	1446
values[0x0]	23105	1		T1	24		T2	177		T3	697
values[0x1]	24011	1		T1	27		T2	165		T3	748

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	39402	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	79590	1		T1	120		T2	508		T3	1773

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	462	1		T3	7		T17	1		T4	2
valid_sources[0x01]	971	1		T3	11		T17	3		T4	2
valid_sources[0x02]	565	1		T3	13		T6	11		T4	2
valid_sources[0x03]	628	1		T2	8		T3	9		T6	2
valid_sources[0x04]	441	1		T3	7		T4	1		T32	15
valid_sources[0x05]	343	1		T3	7		T6	2		T5	8
valid_sources[0x06]	359	1		T2	2		T3	14		T17	5
valid_sources[0x07]	372	1		T3	10		T4	1		T5	1
valid_sources[0x08]	529	1		T3	8		T4	3		T5	8
valid_sources[0x09]	439	1		T2	5		T3	14		T6	2
valid_sources[0x0a]	402	1		T3	9		T18	25		T4	3
valid_sources[0x0b]	500	1		T2	10		T3	12		T19	2
valid_sources[0x0c]	499	1		T2	6		T3	9		T4	2
valid_sources[0x0d]	511	1		T3	9		T18	7		T17	3
valid_sources[0x0e]	421	1		T3	16		T4	2		T5	4
valid_sources[0x0f]	467	1		T3	19		T5	5		T20	2
valid_sources[0x10]	521	1		T3	16		T5	2		T19	2
valid_sources[0x11]	422	1		T3	14		T4	3		T5	3
valid_sources[0x12]	462	1		T2	5		T3	16		T17	1
valid_sources[0x13]	653	1		T3	12		T4	2		T5	6
valid_sources[0x14]	538	1		T2	1		T3	18		T6	19
valid_sources[0x15]	581	1		T3	10		T4	2		T5	1
valid_sources[0x16]	408	1		T3	4		T6	20		T4	2
valid_sources[0x17]	541	1		T2	14		T3	11		T6	2
valid_sources[0x18]	358	1		T2	3		T3	9		T5	5
valid_sources[0x19]	390	1		T2	5		T3	15		T4	1
valid_sources[0x1a]	341	1		T2	4		T3	18		T4	1
valid_sources[0x1b]	785	1		T2	4		T3	9		T6	1
valid_sources[0x1c]	359	1		T2	4		T3	9		T5	2
valid_sources[0x1d]	484	1		T1	68		T2	2		T3	14
valid_sources[0x1e]	467	1		T3	19		T17	1		T5	5
valid_sources[0x1f]	362	1		T3	12		T19	2		T28	1
valid_sources[0x20]	492	1		T3	6		T18	2		T4	3
valid_sources[0x21]	333	1		T3	12		T4	1		T5	4
valid_sources[0x22]	392	1		T3	12		T18	8		T17	1
valid_sources[0x23]	459	1		T3	10		T6	1		T17	1
valid_sources[0x24]	418	1		T3	17		T18	1		T5	5
valid_sources[0x25]	392	1		T3	12		T6	7		T18	8
valid_sources[0x26]	433	1		T3	10		T18	2		T5	4
valid_sources[0x27]	396	1		T2	14		T3	9		T4	1
valid_sources[0x28]	374	1		T2	3		T3	16		T4	1
valid_sources[0x29]	383	1		T3	10		T5	14		T32	15
valid_sources[0x2a]	417	1		T3	16		T6	5		T4	1
valid_sources[0x2b]	470	1		T2	10		T3	9		T5	6
valid_sources[0x2c]	411	1		T2	3		T3	12		T18	11
valid_sources[0x2d]	399	1		T3	12		T4	1		T5	4
valid_sources[0x2e]	491	1		T2	4		T3	13		T5	2
valid_sources[0x2f]	601	1		T2	10		T3	8		T6	18
valid_sources[0x30]	411	1		T3	10		T6	2		T17	2
valid_sources[0x31]	373	1		T3	12		T17	1		T4	1
valid_sources[0x32]	389	1		T3	16		T4	1		T5	1
valid_sources[0x33]	483	1		T3	15		T17	3		T4	1
valid_sources[0x34]	360	1		T2	5		T3	9		T5	6
valid_sources[0x35]	437	1		T2	2		T3	11		T6	2
valid_sources[0x36]	418	1		T3	5		T6	5		T4	2
valid_sources[0x37]	317	1		T3	11		T5	1		T19	5
valid_sources[0x38]	540	1		T2	2		T3	15		T18	11
valid_sources[0x39]	316	1		T3	8		T4	2		T32	14
valid_sources[0x3a]	425	1		T2	17		T3	15		T18	11
valid_sources[0x3b]	323	1		T3	11		T6	3		T18	6
valid_sources[0x3c]	409	1		T3	11		T6	3		T4	2
valid_sources[0x3d]	417	1		T2	10		T3	8		T4	4
valid_sources[0x3e]	514	1		T3	11		T6	9		T17	1
valid_sources[0x3f]	663	1		T2	9		T3	8		T4	3
valid_sources[0x40]	423	1		T3	11		T18	3		T4	4
valid_sources[0x41]	416	1		T3	14		T18	1		T4	2
valid_sources[0x42]	408	1		T3	10		T17	1		T5	9
valid_sources[0x43]	431	1		T2	4		T3	20		T4	1
valid_sources[0x44]	359	1		T3	10		T18	7		T5	3
valid_sources[0x45]	497	1		T2	1		T3	14		T17	2
valid_sources[0x46]	504	1		T2	7		T3	7		T5	3
valid_sources[0x47]	434	1		T2	4		T3	8		T17	1
valid_sources[0x48]	388	1		T3	12		T4	2		T5	2
valid_sources[0x49]	422	1		T3	7		T4	1		T5	3
valid_sources[0x4a]	374	1		T3	12		T6	10		T5	3
valid_sources[0x4b]	316	1		T2	3		T3	7		T4	1
valid_sources[0x4c]	453	1		T3	15		T18	7		T17	1
valid_sources[0x4d]	438	1		T3	9		T17	2		T4	1
valid_sources[0x4e]	457	1		T2	2		T3	9		T4	2
valid_sources[0x4f]	486	1		T2	1		T3	9		T18	3
valid_sources[0x50]	336	1		T3	12		T18	14		T4	1
valid_sources[0x51]	725	1		T2	11		T3	17		T6	9
valid_sources[0x52]	438	1		T2	15		T3	15		T17	1
valid_sources[0x53]	705	1		T2	2		T3	8		T5	2
valid_sources[0x54]	393	1		T3	11		T6	5		T4	1
valid_sources[0x55]	402	1		T2	1		T3	13		T6	17
valid_sources[0x56]	405	1		T3	10		T6	10		T5	3
valid_sources[0x57]	446	1		T2	13		T3	9		T18	5
valid_sources[0x58]	384	1		T3	8		T6	1		T5	3
valid_sources[0x59]	371	1		T2	1		T3	14		T6	2
valid_sources[0x5a]	378	1		T2	4		T3	15		T4	2
valid_sources[0x5b]	386	1		T3	12		T4	1		T19	2
valid_sources[0x5c]	491	1		T2	6		T3	11		T6	4
valid_sources[0x5d]	522	1		T2	6		T3	9		T6	7
valid_sources[0x5e]	367	1		T3	12		T6	2		T18	2
valid_sources[0x5f]	345	1		T3	11		T4	2		T5	3
valid_sources[0x60]	541	1		T2	6		T3	11		T18	9
valid_sources[0x61]	417	1		T2	12		T3	6		T6	4
valid_sources[0x62]	359	1		T3	12		T17	2		T4	1
valid_sources[0x63]	498	1		T2	21		T3	15		T5	2
valid_sources[0x64]	563	1		T3	13		T18	4		T17	1
valid_sources[0x65]	680	1		T2	6		T3	11		T18	2
valid_sources[0x66]	533	1		T3	10		T17	1		T4	1
valid_sources[0x67]	384	1		T3	19		T4	2		T5	5
valid_sources[0x68]	446	1		T3	13		T6	17		T18	2
valid_sources[0x69]	499	1		T2	6		T3	5		T6	6
valid_sources[0x6a]	500	1		T3	11		T17	1		T4	1
valid_sources[0x6b]	522	1		T2	17		T3	6		T4	4
valid_sources[0x6c]	429	1		T3	8		T6	16		T4	1
valid_sources[0x6d]	440	1		T3	9		T18	4		T17	1
valid_sources[0x6e]	491	1		T3	11		T6	7		T17	1
valid_sources[0x6f]	353	1		T3	12		T6	1		T5	1
valid_sources[0x70]	427	1		T3	11		T6	9		T18	6
valid_sources[0x71]	413	1		T2	1		T3	8		T18	11
valid_sources[0x72]	451	1		T3	12		T18	1		T4	4
valid_sources[0x73]	342	1		T2	1		T3	5		T17	1
valid_sources[0x74]	385	1		T2	7		T3	8		T6	1
valid_sources[0x75]	407	1		T3	7		T5	1		T20	7
valid_sources[0x76]	374	1		T2	3		T3	11		T6	1
valid_sources[0x77]	370	1		T3	14		T4	2		T5	7
valid_sources[0x78]	387	1		T3	11		T4	1		T5	11
valid_sources[0x79]	542	1		T2	10		T3	16		T4	1
valid_sources[0x7a]	391	1		T2	5		T3	10		T6	2
valid_sources[0x7b]	492	1		T2	13		T3	12		T6	4
valid_sources[0x7c]	456	1		T3	17		T5	1		T19	2
valid_sources[0x7d]	448	1		T3	11		T6	3		T18	1
valid_sources[0x7e]	406	1		T3	11		T18	4		T17	5
valid_sources[0x7f]	515	1		T2	1		T3	8		T18	5
valid_sources[0x80]	358	1		T3	13		T6	2		T4	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

23806

1

T1

11

T2

61

T3

707

values[0x0]

all_enables

biggest_size

19828

1

T1

18

T2

170

T3

448

values[0x1]

all_enables

biggest_size

17758

1

T1

15

T2

149

T3

305