Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	73356	1		T1	242		T2	373		T3	1431
full_word	62518	1		T1	44		T2	380		T3	1460

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	135594	1		T1	286		T2	753		T3	2891
auto[TlIntgErrCmd]	98	1		T26	2		T30	7		T29	7
auto[TlIntgErrData]	104	1		T26	3		T30	7		T29	10
auto[TlIntgErrBoth]	78	1		T26	5		T30	6		T29	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	73924	1		T1	235		T2	392		T3	1446
auto[1]	61950	1		T1	51		T2	361		T3	1445

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	49795	1		T1	224		T2	331		T3	739
auto[TlIntgErrNone]	partial	auto[1]	23314	1		T1	18		T2	42		T3	692
auto[TlIntgErrNone]	full_word	auto[0]	23989	1		T1	11		T2	61		T3	707
auto[TlIntgErrNone]	full_word	auto[1]	38496	1		T1	33		T2	319		T3	753
auto[TlIntgErrCmd]	partial	auto[0]	37	1		T26	1		T30	2		T29	3
auto[TlIntgErrCmd]	partial	auto[1]	52	1		T26	1		T30	5		T29	3
auto[TlIntgErrCmd]	full_word	auto[0]	5	1		T53	1		T69	2		T71	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T29	1		T68	1		T69	1
auto[TlIntgErrData]	partial	auto[0]	53	1		T26	2		T30	4		T29	6
auto[TlIntgErrData]	partial	auto[1]	37	1		T26	1		T30	2		T29	3
auto[TlIntgErrData]	full_word	auto[0]	9	1		T29	1		T69	1		T57	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T30	1		T69	1		T72	1
auto[TlIntgErrBoth]	partial	auto[0]	31	1		T26	2		T30	3		T68	1
auto[TlIntgErrBoth]	partial	auto[1]	37	1		T26	1		T30	1		T29	3
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T26	1		T68	1		T69	1
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T26	1		T30	2		T68	1