Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
22.73	0.00	0.00	90.91		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1714355	12790	0	0
ep_in_enable_rd_A	1714355	2747	0	0
ep_out_enable_rd_A	1714355	2825	0	0
in_iso_rd_A	1714355	3241	0	0
intr_enable_rd_A	1714355	4201	0	0
out_iso_rd_A	1714355	2544	0	0
phy_config_rd_A	1714355	1544	0	0
phy_pins_drive_rd_A	1714355	2434	0	0
rxenable_setup_rd_A	1714355	2568	0	0
set_nak_out_rd_A	1714355	2654	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714355	12790	0	0
T2	11098	9	0	0
T3	38993	0	0	0
T4	4488	7	0	0
T5	3934	14	0	0
T6	14018	758	0	0
T16	1589	0	0	0
T17	4039	0	0	0
T18	3571	0	0	0
T19	2650	0	0	0
T20	3511	0	0	0
T21	0	7	0	0
T22	0	918	0	0
T23	0	232	0	0
T25	0	36	0	0
T26	0	3	0	0
T30	0	5	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714355	2747	0	0
T2	11098	116	0	0
T3	38993	116	0	0
T4	4488	13	0	0
T5	3934	0	0	0
T6	14018	0	0	0
T16	1589	0	0	0
T17	4039	0	0	0
T18	3571	0	0	0
T19	2650	0	0	0
T20	3511	0	0	0
T28	0	1	0	0
T30	0	566	0	0
T35	0	44	0	0
T53	0	90	0	0
T56	0	61	0	0
T57	0	528	0	0
T58	0	118	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714355	2825	0	0
T2	11098	56	0	0
T3	38993	179	0	0
T4	4488	4	0	0
T5	3934	0	0	0
T6	14018	0	0	0
T16	1589	0	0	0
T17	4039	0	0	0
T18	3571	0	0	0
T19	2650	0	0	0
T20	3511	0	0	0
T22	0	1	0	0
T28	0	39	0	0
T30	0	578	0	0
T35	0	74	0	0
T53	0	63	0	0
T56	0	27	0	0
T57	0	472	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714355	3241	0	0
T2	11098	92	0	0
T3	38993	99	0	0
T4	4488	53	0	0
T5	3934	0	0	0
T6	14018	0	0	0
T16	1589	0	0	0
T17	4039	0	0	0
T18	3571	0	0	0
T19	2650	0	0	0
T20	3511	0	0	0
T22	0	4	0	0
T28	0	9	0	0
T30	0	721	0	0
T35	0	42	0	0
T53	0	198	0	0
T56	0	31	0	0
T57	0	557	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714355	4201	0	0
T2	11098	98	0	0
T3	38993	177	0	0
T4	4488	74	0	0
T5	3934	0	0	0
T6	14018	0	0	0
T12	0	3	0	0
T13	0	15	0	0
T14	0	6	0	0
T16	1589	0	0	0
T17	4039	0	0	0
T18	3571	0	0	0
T19	2650	0	0	0
T20	3511	0	0	0
T22	0	14	0	0
T28	0	58	0	0
T30	0	808	0	0
T35	0	75	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714355	2544	0	0
T2	11098	48	0	0
T3	38993	116	0	0
T4	4488	59	0	0
T5	3934	0	0	0
T6	14018	0	0	0
T16	1589	0	0	0
T17	4039	0	0	0
T18	3571	0	0	0
T19	2650	0	0	0
T20	3511	0	0	0
T22	0	2	0	0
T28	0	62	0	0
T30	0	433	0	0
T35	0	41	0	0
T53	0	119	0	0
T56	0	46	0	0
T57	0	491	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714355	1544	0	0
T2	11098	13	0	0
T3	38993	130	0	0
T4	4488	8	0	0
T5	3934	0	0	0
T6	14018	0	0	0
T16	1589	0	0	0
T17	4039	0	0	0
T18	3571	0	0	0
T19	2650	0	0	0
T20	3511	0	0	0
T28	0	19	0	0
T30	0	287	0	0
T35	0	32	0	0
T53	0	61	0	0
T56	0	39	0	0
T57	0	239	0	0
T58	0	109	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714355	2434	0	0
T2	11098	63	0	0
T3	38993	98	0	0
T4	4488	5	0	0
T5	3934	0	0	0
T6	14018	0	0	0
T16	1589	0	0	0
T17	4039	0	0	0
T18	3571	0	0	0
T19	2650	0	0	0
T20	3511	0	0	0
T28	0	31	0	0
T30	0	479	0	0
T35	0	6	0	0
T53	0	99	0	0
T56	0	16	0	0
T57	0	573	0	0
T58	0	131	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714355	2568	0	0
T2	11098	115	0	0
T3	38993	112	0	0
T4	4488	6	0	0
T5	3934	0	0	0
T6	14018	7	0	0
T16	1589	0	0	0
T17	4039	0	0	0
T18	3571	0	0	0
T19	2650	0	0	0
T20	3511	0	0	0
T28	0	45	0	0
T30	0	548	0	0
T35	0	54	0	0
T53	0	167	0	0
T56	0	4	0	0
T57	0	461	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714355	2654	0	0
T2	11098	22	0	0
T3	38993	120	0	0
T4	4488	10	0	0
T5	3934	0	0	0
T6	14018	0	0	0
T16	1589	0	0	0
T17	4039	0	0	0
T18	3571	0	0	0
T19	2650	0	0	0
T20	3511	0	0	0
T28	0	6	0	0
T30	0	607	0	0
T35	0	60	0	0
T53	0	152	0	0
T56	0	23	0	0
T57	0	518	0	0
T58	0	118	0	0