Unified Coverage Report :: Module :: usb_fs_nb_pe

Module : usb_fs_nb_pe

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_pe.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.28	99.24	96.56		97.06	98.53	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.40	100.00	97.59			100.00	100.00	usbdev_impl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_usb_fs_nb_in_pe	96.14	98.32	95.61		90.91	95.83	100.00
u_usb_fs_nb_out_pe	97.42	97.64	93.28		100.00	96.15	100.00
u_usb_fs_rx	99.51	100.00	98.54			100.00
u_usb_fs_tx	99.63	100.00	98.15		100.00	100.00	100.00
u_usb_fs_tx_mux	100.00	100.00	100.00			100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : usb_fs_nb_pe

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	166	1	1	100.00
CONT_ASSIGN	169	1	1	100.00
CONT_ASSIGN	171	1	1	100.00
CONT_ASSIGN	172	1	1	100.00
CONT_ASSIGN	176	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_pe.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
166	1	1
169	1	1
171	1	1
172	1	1
176	1	1

---

Cond Coverage for Module : usb_fs_nb_pe

	Total	Covered	Percent
Conditions	12	12	100.00
Logical	12	12	100.00
Non-Logical	0	0
Event	0	0

 LINE       166
 EXPRESSION (rx_pkt_end & rx_pid_valid & (usb_pid_e'(rx_pid) == UsbPidSof))
             -----1----   ------2-----   ----------------3----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T84,T85,T86
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T26,T94,T6

 LINE       166
 SUB-EXPRESSION (usb_pid_e'(rx_pid) == UsbPidSof)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       169
 EXPRESSION (rx_pkt_end & rx_pkt_valid & (usb_pid_e'(rx_pid) == UsbPidSof))
             -----1----   ------2-----   ----------------3----------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T26,T94,T6
1	0	1	Covered	T84,T85,T86
1	1	0	Covered	T1,T2,T3
1	1	1	Covered	T26,T94,T6

 LINE       169
 SUB-EXPRESSION (usb_pid_e'(rx_pid) == UsbPidSof)
                ----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Assert Coverage for Module : usb_fs_nb_pe

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumOutEpsEqualsNumInEps_A	3564	3564	0	0
ParamMaxPktSizeByteValid	3564	3564	0	0
ParamNumEpsOutAndInEqual	3564	3564	0	0
ParamNumInEpsValid	3564	3564	0	0
ParamNumOutEpsValid	3564	3564	0	0

NumOutEpsEqualsNumInEps_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3564	3564	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T34	1	1	0	0

ParamMaxPktSizeByteValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	3564	3564	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T34	1	1	0	0

ParamNumEpsOutAndInEqual

Name	Attempts	Real Successes	Failures	Incomplete
Total	3564	3564	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T34	1	1	0	0

ParamNumInEpsValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	3564	3564	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T34	1	1	0	0

ParamNumOutEpsValid

Name	Attempts	Real Successes	Failures	Incomplete
Total	3564	3564	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T26	1	1	0	0
T27	1	1	0	0
T28	1	1	0	0
T29	1	1	0	0
T30	1	1	0	0
T31	1	1	0	0
T34	1	1	0	0