Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : usb_fs_nb_out_pe
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.05 97.64 93.28 100.00 94.34 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe 97.42 97.64 93.28 100.00 96.15 100.00



Module Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.42 97.64 93.28 100.00 96.15 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.42 97.64 93.28 100.00 96.15 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_usb_fs_nb_pe


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : usb_fs_nb_out_pe
Line No.TotalCoveredPercent
TOTAL12712497.64
CONT_ASSIGN9011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17811100.00
ALWAYS18466100.00
ALWAYS19644100.00
ALWAYS212555294.55
CONT_ASSIGN32611100.00
ALWAYS32933100.00
ALWAYS33733100.00
ALWAYS34677100.00
CONT_ASSIGN36011100.00
ALWAYS36355100.00
ALWAYS37399100.00
ALWAYS39033100.00
ALWAYS40266100.00
CONT_ASSIGN41811100.00
ALWAYS42166100.00
CONT_ASSIGN43511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
90 1 1
131 1 1
132 1 1
134 1 1
140 1 1
144 1 1
148 1 1
152 1 1
157 1 1
163 1 1
164 1 1
171 1 1
172 1 1
175 1 1
176 1 1
178 1 1
184 1 1
185 1 1
187 1 1
188 1 1
189 1 1
190 1 1
MISSING_ELSE
196 1 1
197 1 1
199 1 1
200 1 1
MISSING_ELSE
212 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
221 1 1
225 1 1
226 1 1
227 1 1
229 1 1
237 1 1
239 1 1
240 1 1
241 1 1
242 1 1
244 1 1
249 1 1
253 1 1
254 1 1
257 1 1
258 1 1
259 1 1
260 1 1
261 1 1
263 1 1
264 1 1
265 1 1
266 1 1
268 1 1
273 1 1
274 1 1
276 1 1
278 1 1
280 0 1
281 0 1
283 1 1
284 1 1
285 1 1
289 1 1
290 1 1
291 1 1
292 1 1
293 1 1
294 1 1
296 1 1
297 1 1
298 1 1
305 1 1
307 1 1
309 0 1
312 1 1
313 1 1
326 1 1
329 1 1
330 1 1
332 1 1
337 1 1
338 1 1
340 1 1
346 1 1
348 1 1
349 1 1
350 1 1
351 1 1
MISSING_ELSE
354 1 1
355 1 1
MISSING_ELSE
360 1 1
363 1 1
364 1 1
365 1 1
366 1 1
368 1 1
373 1 1
374 1 1
375 1 1
376 1 1
378 1 1
379 1 1
380 1 1
381 1 1
383 1 1
390 1 1
391 1 1
393 1 1
402 1 1
403 1 1
405 1 1
406 1 1
407 1 1
408 1 1
MISSING_ELSE
418 1 1
421 1 1
422 1 1
424 1 1
425 1 1
426 1 1
427 1 1
MISSING_ELSE
435 1 1


Cond Coverage for Module : usb_fs_nb_out_pe
TotalCoveredPercent
Conditions13412593.28
Logical13412593.28
Non-Logical00
Event00

 LINE       134
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
             ------1-----    -------2------    ----------------3---------------    ------------4------------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT71,T74,T105
1101CoveredT1,T2,T3
1110CoveredT26,T27,T106
1111CoveredT1,T2,T3

 LINE       134
 SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       134
 SUB-EXPRESSION (rx_addr_i == dev_addr_i)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (token_received && (rx_pid == UsbPidOut))
             -------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       140
 SUB-EXPRESSION (rx_pid == UsbPidOut)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 EXPRESSION (token_received && (rx_pid == UsbPidSetup))
             -------1------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T34,T27
10CoveredT1,T2,T3
11CoveredT1,T34,T27

 LINE       144
 SUB-EXPRESSION (rx_pid == UsbPidSetup)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T34,T27

 LINE       148
 EXPRESSION (rx_pkt_end_i && ((!rx_pkt_valid_i)))
             ------1-----    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT27,T69,T70

 LINE       152
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)))
             ------1-----    -------2------    --------------------------3-------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT69,T70,T72
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T26
10CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T26

 LINE       157
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) ))
             ------1-----    -------2------    -----------------------------3----------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT27,T106,T71
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) )
                    --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T26
10CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T26

 LINE       164
 EXPRESSION (ep_in_hw ? rx_endp_i : '0)
             ----1---
-1-StatusTests
0CoveredT26,T27,T106
1CoveredT1,T2,T3

 LINE       175
 EXPRESSION (out_ep_enabled_i[out_ep_index_d] & ep_in_hw)
             ----------------1---------------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT27,T106,T18
11CoveredT1,T2,T3

 LINE       178
 EXPRESSION (data_packet_received && ep_active && (rx_pid_i[3] != data_toggle_q[out_ep_index_d]))
             ----------1---------    ----2----    -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT154,T150,T111
110CoveredT1,T2,T3
111CoveredT1,T2,T27

 LINE       178
 SUB-EXPRESSION (rx_pid_i[3] != data_toggle_q[out_ep_index_d])
                -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       187
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT27,T110,T111
11CoveredT1,T34,T27

 LINE       189
 EXPRESSION (out_token_received && ep_active)
             ---------1--------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT27,T154,T150
11CoveredT1,T2,T3

 LINE       225
 EXPRESSION (ep_active && (out_token_received || (setup_token_received && ep_is_control)))
             ----1----    -------------------------------2-------------------------------
-1--2-StatusTests
01CoveredT27,T154,T150
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       225
 SUB-EXPRESSION (out_token_received || (setup_token_received && ep_is_control))
                 ---------1--------    -------------------2-------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T27,T29
10CoveredT1,T2,T3

 LINE       225
 SUB-EXPRESSION (setup_token_received && ep_is_control)
                 ----------1---------    ------2------
-1--2-StatusTests
01CoveredT1,T27,T29
10CoveredT34,T27,T19
11CoveredT1,T27,T29

 LINE       241
 EXPRESSION (timeout_cntdown_q == '0)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT246

 LINE       249
 EXPRESSION (((!ep_is_control)) && out_ep_iso_i[out_ep_index] && data_packet_received)
             ---------1--------    -------------2------------    ----------3---------
-1--2--3-StatusTests
011CoveredT1,T4,T61
101CoveredT1,T2,T3
110CoveredT1,T4,T247
111CoveredT1,T4,T247

 LINE       254
 EXPRESSION (bad_data_toggle && ((!out_ep_stall_i[out_ep_index])))
             -------1-------    ----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T28,T107

 LINE       261
 EXPRESSION (invalid_packet_received || non_data_packet_received)
             -----------1-----------    ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT85,T86
10CoveredT69,T70,T72

 LINE       278
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT1,T27,T29
01Not Covered
10Not Covered

 LINE       292
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       307
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T247
01Not Covered
10Not Covered

 LINE       340
 EXPRESSION (link_reset_i ? StIdle : out_xact_state_next)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       348
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT27,T110,T111
11CoveredT1,T34,T27

 LINE       393
 EXPRESSION ((out_xact_state == StRcvdDataStart) && rx_data_put_i)
             -----------------1-----------------    ------2------
-1--2-StatusTests
01CoveredT34,T27,T106
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       393
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION ((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))
             -------------1------------    --------------2--------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       405
 SUB-EXPRESSION (out_xact_state == StIdle)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 SUB-EXPRESSION (out_xact_state == StRcvdOut)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       407
 EXPRESSION (out_ep_data_put_o && out_ep_full_i[out_ep_index])
             --------1--------    -------------2-------------
-1--2-StatusTests
01CoveredT27,T29,T70
10CoveredT1,T2,T3
11CoveredT27,T70,T134

 LINE       418
 EXPRESSION (((!nak_out_transaction)) && ((~&out_ep_put_addr_o)) && out_ep_data_put_o)
             ------------1-----------    -----------2-----------    --------3--------
-1--2--3-StatusTests
011CoveredT27,T70,T134
101CoveredT1,T33,T87
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       424
 EXPRESSION (out_xact_state == StRcvdOut)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       426
 EXPRESSION ((out_xact_state == StRcvdDataStart) && increment_addr)
             -----------------1-----------------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       426
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       435
 EXPRESSION ((out_xact_state == StRcvdDataStart) && (ep_is_control || ((!out_ep_iso_i[out_ep_index]))) && ((!out_ep_stall_i[out_ep_index])) && bad_data_toggle)
             -----------------1-----------------    -------------------------2------------------------    ----------------3----------------    -------4-------
-1--2--3--4-StatusTests
0111CoveredT27,T110,T111
1011CoveredT1,T4,T61
1101Not Covered
1110CoveredT1,T2,T3
1111CoveredT2,T28,T107

 LINE       435
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       435
 SUB-EXPRESSION (ep_is_control || ((!out_ep_iso_i[out_ep_index])))
                 ------1------    ---------------2---------------
-1--2-StatusTests
00CoveredT1,T106,T4
01CoveredT1,T2,T3
10CoveredT1,T106,T4

FSM Coverage for Module : usb_fs_nb_out_pe
Summary for FSM :: out_xact_state
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 8 8 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: out_xact_state
states   Line No.   Covered   Tests   
StIdle 340 Covered T1,T2,T3
StRcvdDataEnd 266 Covered T1,T2,T3
StRcvdDataStart 240 Covered T1,T2,T3
StRcvdIsoDataEnd 253 Covered T1,T4,T247
StRcvdOut 226 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
StIdle->StRcvdOut 226 Covered T1,T2,T3
StRcvdDataEnd->StIdle 340 Covered T1,T2,T3
StRcvdDataStart->StIdle 340 Covered T2,T28,T29
StRcvdDataStart->StRcvdDataEnd 266 Covered T1,T2,T3
StRcvdDataStart->StRcvdIsoDataEnd 253 Covered T1,T4,T247
StRcvdIsoDataEnd->StIdle 340 Covered T1,T4,T247
StRcvdOut->StIdle 340 Covered T246
StRcvdOut->StRcvdDataStart 240 Covered T1,T2,T3



Branch Coverage for Module : usb_fs_nb_out_pe
Line No.TotalCoveredPercent
Branches 53 50 94.34
TERNARY 164 2 2 100.00
IF 184 4 4 100.00
IF 196 3 3 100.00
CASE 221 18 15 83.33
IF 329 2 2 100.00
IF 337 3 3 100.00
IF 348 3 3 100.00
IF 354 2 2 100.00
IF 363 3 3 100.00
IF 373 3 3 100.00
IF 390 2 2 100.00
IF 402 4 4 100.00
IF 421 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 164 (ep_in_hw) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T26,T27,T106


LineNo. Expression -1-: 184 if ((!rst_ni)) -2-: 187 if ((setup_token_received && ep_active)) -3-: 189 if ((out_token_received && ep_active))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T34,T27
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 196 if ((!rst_ni)) -2-: 199 if (rx_data_put_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 221 case (out_xact_state) -2-: 225 if ((ep_active && (out_token_received || (setup_token_received && ep_is_control)))) -3-: 239 if (rx_pkt_start_i) -4-: 241 if ((timeout_cntdown_q == '0)) -5-: 249 if ((((!ep_is_control) && out_ep_iso_i[out_ep_index]) && data_packet_received)) -6-: 254 if ((bad_data_toggle && (!out_ep_stall_i[out_ep_index]))) -7-: 261 if ((invalid_packet_received || non_data_packet_received)) -8-: 265 if (data_packet_received) -9-: 276 if (current_xact_setup_q) -10-: 278 if ((nak_out_transaction | out_ep_full_i[out_ep_index])) -11-: 289 if (out_ep_stall_i[out_ep_index]) -12-: 292 if ((nak_out_transaction | out_ep_full_i[out_ep_index])) -13-: 307 if ((nak_out_transaction | out_ep_full_i[out_ep_index]))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13-StatusTests
StIdle 1 - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 - - - - - - - - - - - Covered T1,T2,T3
StRcvdOut - 1 - - - - - - - - - - Covered T1,T2,T3
StRcvdOut - 0 1 - - - - - - - - - Covered T246
StRcvdOut - 0 0 - - - - - - - - - Covered T1,T2,T3
StRcvdDataStart - - - 1 - - - - - - - - Covered T1,T4,T247
StRcvdDataStart - - - 0 1 - - - - - - - Covered T2,T28,T107
StRcvdDataStart - - - 0 0 1 - - - - - - Covered T69,T70,T72
StRcvdDataStart - - - 0 0 0 1 - - - - - Covered T1,T2,T3
StRcvdDataStart - - - 0 0 0 0 - - - - - Covered T1,T2,T3
StRcvdDataEnd - - - - - - - 1 1 - - - Not Covered
StRcvdDataEnd - - - - - - - 1 0 - - - Covered T1,T27,T29
StRcvdDataEnd - - - - - - - 0 - 1 - - Covered T27,T32,T248
StRcvdDataEnd - - - - - - - 0 - 0 1 - Covered T134,T118,T110
StRcvdDataEnd - - - - - - - 0 - 0 0 - Covered T1,T2,T3
StRcvdIsoDataEnd - - - - - - - - - - - 1 Not Covered
StRcvdIsoDataEnd - - - - - - - - - - - 0 Covered T1,T4,T247
default - - - - - - - - - - - - Not Covered


LineNo. Expression -1-: 329 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 337 if ((!rst_ni)) -2-: 340 (link_reset_i) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 348 if ((setup_token_received && ep_active)) -2-: 350 if (new_pkt_end)

Branches:
-1--2-StatusTests
1 - Covered T1,T34,T27
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 354 if (out_datatog_we_i)

Branches:
-1-StatusTests
1 Covered T2,T28,T107
0 Covered T1,T2,T3


LineNo. Expression -1-: 363 if ((!rst_ni)) -2-: 365 if (link_reset_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 373 if ((!rst_ni)) -2-: 378 if (out_xact_start)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 390 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 402 if ((!rst_ni)) -2-: 405 if (((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))) -3-: 407 if ((out_ep_data_put_o && out_ep_full_i[out_ep_index]))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T27,T70,T134
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 421 if ((!rst_ni)) -2-: 424 if ((out_xact_state == StRcvdOut)) -3-: 426 if (((out_xact_state == StRcvdDataStart) && increment_addr))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : usb_fs_nb_out_pe
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutXactStateValid_A 577955159 577670942 0 0


OutXactStateValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577955159 577670942 0 0
T1 135399 135303 0 0
T2 27389 27301 0 0
T3 11323 11267 0 0
T26 615265 615183 0 0
T27 223214 223209 0 0
T28 36183 36118 0 0
T29 22688 22615 0 0
T30 9845 9776 0 0
T31 64585 64529 0 0
T34 7411 7339 0 0

Line Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe
Line No.TotalCoveredPercent
TOTAL12712497.64
CONT_ASSIGN9011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
CONT_ASSIGN14411100.00
CONT_ASSIGN14811100.00
CONT_ASSIGN15211100.00
CONT_ASSIGN15711100.00
CONT_ASSIGN16311100.00
CONT_ASSIGN16411100.00
CONT_ASSIGN17111100.00
CONT_ASSIGN17211100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN17811100.00
ALWAYS18466100.00
ALWAYS19644100.00
ALWAYS212555294.55
CONT_ASSIGN32611100.00
ALWAYS32933100.00
ALWAYS33733100.00
ALWAYS34677100.00
CONT_ASSIGN36011100.00
ALWAYS36355100.00
ALWAYS37399100.00
ALWAYS39033100.00
ALWAYS40266100.00
CONT_ASSIGN41811100.00
ALWAYS42166100.00
CONT_ASSIGN43511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
90 1 1
131 1 1
132 1 1
134 1 1
140 1 1
144 1 1
148 1 1
152 1 1
157 1 1
163 1 1
164 1 1
171 1 1
172 1 1
175 1 1
176 1 1
178 1 1
184 1 1
185 1 1
187 1 1
188 1 1
189 1 1
190 1 1
MISSING_ELSE
196 1 1
197 1 1
199 1 1
200 1 1
MISSING_ELSE
212 1 1
213 1 1
214 1 1
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
221 1 1
225 1 1
226 1 1
227 1 1
229 1 1
237 1 1
239 1 1
240 1 1
241 1 1
242 1 1
244 1 1
249 1 1
253 1 1
254 1 1
257 1 1
258 1 1
259 1 1
260 1 1
261 1 1
263 1 1
264 1 1
265 1 1
266 1 1
268 1 1
273 1 1
274 1 1
276 1 1
278 1 1
280 0 1
281 0 1
283 1 1
284 1 1
285 1 1
289 1 1
290 1 1
291 1 1
292 1 1
293 1 1
294 1 1
296 1 1
297 1 1
298 1 1
305 1 1
307 1 1
309 0 1
312 1 1
313 1 1
Exclude Annotation: VC_COV_UNR
326 1 1
329 1 1
330 1 1
332 1 1
337 1 1
338 1 1
340 1 1
346 1 1
348 1 1
349 1 1
350 1 1
351 1 1
MISSING_ELSE
354 1 1
355 1 1
MISSING_ELSE
360 1 1
363 1 1
364 1 1
365 1 1
366 1 1
368 1 1
373 1 1
374 1 1
375 1 1
376 1 1
378 1 1
379 1 1
380 1 1
381 1 1
383 1 1
390 1 1
391 1 1
393 1 1
402 1 1
403 1 1
405 1 1
406 1 1
407 1 1
408 1 1
MISSING_ELSE
418 1 1
421 1 1
422 1 1
424 1 1
425 1 1
426 1 1
427 1 1
MISSING_ELSE
435 1 1


Cond Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe
TotalCoveredPercent
Conditions13412593.28
Logical13412593.28
Non-Logical00
Event00

 LINE       134
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && (rx_pid_type == UsbPidTypeToken) && (rx_addr_i == dev_addr_i))
             ------1-----    -------2------    ----------------3---------------    ------------4------------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011CoveredT71,T74,T105
1101CoveredT1,T2,T3
1110CoveredT26,T27,T106
1111CoveredT1,T2,T3

 LINE       134
 SUB-EXPRESSION (rx_pid_type == UsbPidTypeToken)
                ----------------1---------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       134
 SUB-EXPRESSION (rx_addr_i == dev_addr_i)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       140
 EXPRESSION (token_received && (rx_pid == UsbPidOut))
             -------1------    ----------2----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       140
 SUB-EXPRESSION (rx_pid == UsbPidOut)
                ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       144
 EXPRESSION (token_received && (rx_pid == UsbPidSetup))
             -------1------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T34,T27
10CoveredT1,T2,T3
11CoveredT1,T34,T27

 LINE       144
 SUB-EXPRESSION (rx_pid == UsbPidSetup)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T34,T27

 LINE       148
 EXPRESSION (rx_pkt_end_i && ((!rx_pkt_valid_i)))
             ------1-----    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT27,T69,T70

 LINE       152
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)))
             ------1-----    -------2------    --------------------------3-------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT69,T70,T72
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T26
10CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       152
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T26

 LINE       157
 EXPRESSION (rx_pkt_end_i && rx_pkt_valid_i && ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) ))
             ------1-----    -------2------    -----------------------------3----------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT27,T106,T71
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION ( ! ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1)) )
                    --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION ((rx_pid == UsbPidData0) || (rx_pid == UsbPidData1))
                 -----------1-----------    -----------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T26
10CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData0)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       157
 SUB-EXPRESSION (rx_pid == UsbPidData1)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T26

 LINE       164
 EXPRESSION (ep_in_hw ? rx_endp_i : '0)
             ----1---
-1-StatusTests
0CoveredT26,T27,T106
1CoveredT1,T2,T3

 LINE       175
 EXPRESSION (out_ep_enabled_i[out_ep_index_d] & ep_in_hw)
             ----------------1---------------   ----2---
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT27,T106,T18
11CoveredT1,T2,T3

 LINE       178
 EXPRESSION (data_packet_received && ep_active && (rx_pid_i[3] != data_toggle_q[out_ep_index_d]))
             ----------1---------    ----2----    -----------------------3----------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT154,T150,T111
110CoveredT1,T2,T3
111CoveredT1,T2,T27

 LINE       178
 SUB-EXPRESSION (rx_pid_i[3] != data_toggle_q[out_ep_index_d])
                -----------------------1----------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       187
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT27,T110,T111
11CoveredT1,T34,T27

 LINE       189
 EXPRESSION (out_token_received && ep_active)
             ---------1--------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT27,T154,T150
11CoveredT1,T2,T3

 LINE       225
 EXPRESSION (ep_active && (out_token_received || (setup_token_received && ep_is_control)))
             ----1----    -------------------------------2-------------------------------
-1--2-StatusTests
01CoveredT27,T154,T150
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       225
 SUB-EXPRESSION (out_token_received || (setup_token_received && ep_is_control))
                 ---------1--------    -------------------2-------------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T27,T29
10CoveredT1,T2,T3

 LINE       225
 SUB-EXPRESSION (setup_token_received && ep_is_control)
                 ----------1---------    ------2------
-1--2-StatusTests
01CoveredT1,T27,T29
10CoveredT34,T27,T19
11CoveredT1,T27,T29

 LINE       241
 EXPRESSION (timeout_cntdown_q == '0)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT246

 LINE       249
 EXPRESSION (((!ep_is_control)) && out_ep_iso_i[out_ep_index] && data_packet_received)
             ---------1--------    -------------2------------    ----------3---------
-1--2--3-StatusTests
011CoveredT1,T4,T61
101CoveredT1,T2,T3
110CoveredT1,T4,T247
111CoveredT1,T4,T247

 LINE       254
 EXPRESSION (bad_data_toggle && ((!out_ep_stall_i[out_ep_index])))
             -------1-------    ----------------2----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT2,T28,T107

 LINE       261
 EXPRESSION (invalid_packet_received || non_data_packet_received)
             -----------1-----------    ------------2-----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT85,T86
10CoveredT69,T70,T72

 LINE       278
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT1,T27,T29
01Not Covered
10Not Covered

 LINE       292
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       307
 EXPRESSION (nak_out_transaction | out_ep_full_i[out_ep_index])
             ---------1---------   -------------2-------------
-1--2-StatusTests
00CoveredT1,T4,T247
01Not Covered
10Not Covered

 LINE       340
 EXPRESSION (link_reset_i ? StIdle : out_xact_state_next)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       348
 EXPRESSION (setup_token_received && ep_active)
             ----------1---------    ----2----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT27,T110,T111
11CoveredT1,T34,T27

 LINE       393
 EXPRESSION ((out_xact_state == StRcvdDataStart) && rx_data_put_i)
             -----------------1-----------------    ------2------
-1--2-StatusTests
01CoveredT34,T27,T106
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       393
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 EXPRESSION ((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))
             -------------1------------    --------------2--------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       405
 SUB-EXPRESSION (out_xact_state == StIdle)
                -------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       405
 SUB-EXPRESSION (out_xact_state == StRcvdOut)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       407
 EXPRESSION (out_ep_data_put_o && out_ep_full_i[out_ep_index])
             --------1--------    -------------2-------------
-1--2-StatusTests
01CoveredT27,T29,T70
10CoveredT1,T2,T3
11CoveredT27,T70,T134

 LINE       418
 EXPRESSION (((!nak_out_transaction)) && ((~&out_ep_put_addr_o)) && out_ep_data_put_o)
             ------------1-----------    -----------2-----------    --------3--------
-1--2--3-StatusTests
011CoveredT27,T70,T134
101CoveredT1,T33,T87
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       424
 EXPRESSION (out_xact_state == StRcvdOut)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       426
 EXPRESSION ((out_xact_state == StRcvdDataStart) && increment_addr)
             -----------------1-----------------    -------2------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       426
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       435
 EXPRESSION ((out_xact_state == StRcvdDataStart) && (ep_is_control || ((!out_ep_iso_i[out_ep_index]))) && ((!out_ep_stall_i[out_ep_index])) && bad_data_toggle)
             -----------------1-----------------    -------------------------2------------------------    ----------------3----------------    -------4-------
-1--2--3--4-StatusTests
0111CoveredT27,T110,T111
1011CoveredT1,T4,T61
1101Not Covered
1110CoveredT1,T2,T3
1111CoveredT2,T28,T107

 LINE       435
 SUB-EXPRESSION (out_xact_state == StRcvdDataStart)
                -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       435
 SUB-EXPRESSION (ep_is_control || ((!out_ep_iso_i[out_ep_index])))
                 ------1------    ---------------2---------------
-1--2-StatusTests
00CoveredT1,T106,T4
01CoveredT1,T2,T3
10CoveredT1,T106,T4

FSM Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe
Summary for FSM :: out_xact_state
TotalCoveredPercent
States 5 5 100.00 (Not included in score)
Transitions 8 8 100.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: out_xact_state
states   Line No.   Covered   Tests   
StIdle 340 Covered T1,T2,T3
StRcvdDataEnd 266 Covered T1,T2,T3
StRcvdDataStart 240 Covered T1,T2,T3
StRcvdIsoDataEnd 253 Covered T1,T4,T247
StRcvdOut 226 Covered T1,T2,T3


transitions   Line No.   Covered   Tests   
StIdle->StRcvdOut 226 Covered T1,T2,T3
StRcvdDataEnd->StIdle 340 Covered T1,T2,T3
StRcvdDataStart->StIdle 340 Covered T2,T28,T29
StRcvdDataStart->StRcvdDataEnd 266 Covered T1,T2,T3
StRcvdDataStart->StRcvdIsoDataEnd 253 Covered T1,T4,T247
StRcvdIsoDataEnd->StIdle 340 Covered T1,T4,T247
StRcvdOut->StIdle 340 Covered T246
StRcvdOut->StRcvdDataStart 240 Covered T1,T2,T3



Branch Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe
Line No.TotalCoveredPercent
Branches 52 50 96.15
TERNARY 164 2 2 100.00
IF 184 4 4 100.00
IF 196 3 3 100.00
CASE 221 17 15 88.24
IF 329 2 2 100.00
IF 337 3 3 100.00
IF 348 3 3 100.00
IF 354 2 2 100.00
IF 363 3 3 100.00
IF 373 3 3 100.00
IF 390 2 2 100.00
IF 402 4 4 100.00
IF 421 4 4 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv' or '../src/lowrisc_ip_usb_fs_nb_pe_0.1/rtl/usb_fs_nb_out_pe.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 164 (ep_in_hw) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T26,T27,T106


LineNo. Expression -1-: 184 if ((!rst_ni)) -2-: 187 if ((setup_token_received && ep_active)) -3-: 189 if ((out_token_received && ep_active))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T34,T27
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 196 if ((!rst_ni)) -2-: 199 if (rx_data_put_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 221 case (out_xact_state) -2-: 225 if ((ep_active && (out_token_received || (setup_token_received && ep_is_control)))) -3-: 239 if (rx_pkt_start_i) -4-: 241 if ((timeout_cntdown_q == '0)) -5-: 249 if ((((!ep_is_control) && out_ep_iso_i[out_ep_index]) && data_packet_received)) -6-: 254 if ((bad_data_toggle && (!out_ep_stall_i[out_ep_index]))) -7-: 261 if ((invalid_packet_received || non_data_packet_received)) -8-: 265 if (data_packet_received) -9-: 276 if (current_xact_setup_q) -10-: 278 if ((nak_out_transaction | out_ep_full_i[out_ep_index])) -11-: 289 if (out_ep_stall_i[out_ep_index]) -12-: 292 if ((nak_out_transaction | out_ep_full_i[out_ep_index])) -13-: 307 if ((nak_out_transaction | out_ep_full_i[out_ep_index]))

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13-StatusTestsExclude Annotation
StIdle 1 - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 - - - - - - - - - - - Covered T1,T2,T3
StRcvdOut - 1 - - - - - - - - - - Covered T1,T2,T3
StRcvdOut - 0 1 - - - - - - - - - Covered T246
StRcvdOut - 0 0 - - - - - - - - - Covered T1,T2,T3
StRcvdDataStart - - - 1 - - - - - - - - Covered T1,T4,T247
StRcvdDataStart - - - 0 1 - - - - - - - Covered T2,T28,T107
StRcvdDataStart - - - 0 0 1 - - - - - - Covered T69,T70,T72
StRcvdDataStart - - - 0 0 0 1 - - - - - Covered T1,T2,T3
StRcvdDataStart - - - 0 0 0 0 - - - - - Covered T1,T2,T3
StRcvdDataEnd - - - - - - - 1 1 - - - Not Covered
StRcvdDataEnd - - - - - - - 1 0 - - - Covered T1,T27,T29
StRcvdDataEnd - - - - - - - 0 - 1 - - Covered T27,T32,T248
StRcvdDataEnd - - - - - - - 0 - 0 1 - Covered T134,T118,T110
StRcvdDataEnd - - - - - - - 0 - 0 0 - Covered T1,T2,T3
StRcvdIsoDataEnd - - - - - - - - - - - 1 Not Covered
StRcvdIsoDataEnd - - - - - - - - - - - 0 Covered T1,T4,T247
default - - - - - - - - - - - - Excluded VC_COV_UNR


LineNo. Expression -1-: 329 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 337 if ((!rst_ni)) -2-: 340 (link_reset_i) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 348 if ((setup_token_received && ep_active)) -2-: 350 if (new_pkt_end)

Branches:
-1--2-StatusTests
1 - Covered T1,T34,T27
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 354 if (out_datatog_we_i)

Branches:
-1-StatusTests
1 Covered T2,T28,T107
0 Covered T1,T2,T3


LineNo. Expression -1-: 363 if ((!rst_ni)) -2-: 365 if (link_reset_i)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 373 if ((!rst_ni)) -2-: 378 if (out_xact_start)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 390 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 402 if ((!rst_ni)) -2-: 405 if (((out_xact_state == StIdle) || (out_xact_state == StRcvdOut))) -3-: 407 if ((out_ep_data_put_o && out_ep_full_i[out_ep_index]))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T27,T70,T134
0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 421 if ((!rst_ni)) -2-: 424 if ((out_xact_state == StRcvdOut)) -3-: 426 if (((out_xact_state == StRcvdDataStart) && increment_addr))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.usbdev_impl.u_usb_fs_nb_pe.u_usb_fs_nb_out_pe
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutXactStateValid_A 577955159 577670942 0 0


OutXactStateValid_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 577955159 577670942 0 0
T1 135399 135303 0 0
T2 27389 27301 0 0
T3 11323 11267 0 0
T26 615265 615183 0 0
T27 223214 223209 0 0
T28 36183 36118 0 0
T29 22688 22615 0 0
T30 9845 9776 0 0
T31 64585 64529 0 0
T34 7411 7339 0 0