Module Definition
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Module : prim_fifo_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.35 100.00 69.42 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.usbdev_avsetupfifo 97.73 100.00 90.91 100.00 100.00
tb.dut.usbdev_avoutfifo 97.73 100.00 90.91 100.00 100.00
tb.dut.usbdev_rxfifo 97.92 100.00 91.67 100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo 100.00 100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo 100.00 100.00 100.00 100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo 100.00 100.00 100.00 100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo 100.00 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :
SCORELINE
97.73 100.00
tb.dut.usbdev_avsetupfifo

SCORELINE
97.73 100.00
tb.dut.usbdev_avoutfifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN14011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
140 1 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Line Coverage for Module self-instances :
SCORELINE
97.92 100.00
tb.dut.usbdev_rxfifo

Line No.TotalCoveredPercent
TOTAL1414100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN12011100.00
ALWAYS12322100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
120 1 1
123 1 1
124 1 1
MISSING_ELSE
133 1 1
134 1 1
138 1 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=108,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 + Width=65,Pass=1,Depth=0,OutputZeroIfEmpty=1,Secure=0,DepthW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.fifo_h.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

SCORELINE
100.00 100.00
tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
44 1 1
45 1 1
48 1 1
49 1 1
53 unreachable

Line Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13411100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
133 1 1
134 1 1
138 1 1

Line Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Line No.TotalCoveredPercent
TOTAL1515100.00
ALWAYS6944100.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10111100.00
CONT_ASSIGN10811100.00
ALWAYS11122100.00
CONT_ASSIGN11611100.00
CONT_ASSIGN13011100.00
CONT_ASSIGN13111100.00
CONT_ASSIGN13811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
69 1 1
70 1 1
71 1 1
72 1 1
MISSING_ELSE
81 1 1
82 1 1
100 1 1
101 1 1
108 1 1
111 1 1
112 1 1
MISSING_ELSE
116 1 1
130 1 1
131 1 1
138 1 1

Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

TotalCoveredPercent
Conditions161062.50
Logical161062.50
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T17,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T17,T18 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T17,T18 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT1,T17,T18 

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T17,T18
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

TotalCoveredPercent
Conditions241875.00
Logical241875.00
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT36,T81,T82
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T17,T18 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T17,T18 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT17,T18,T21
110Not Covered
111CoveredT1,T17,T18 

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T17,T18 

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T17,T18 

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------
-1--2-StatusTests
01CoveredT36,T81,T82
10CoveredT1,T17,T18
11CoveredT1,T2,T3 

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T17,T18
1CoveredT1,T2,T3
Cond Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Cond Coverage for Module self-instances :
SCORECOND
97.73 90.91
tb.dut.usbdev_avsetupfifo

SCORECOND
97.73 90.91
tb.dut.usbdev_avoutfifo

TotalCoveredPercent
Conditions141071.43
Logical141071.43
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T15,T4
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T15 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT52,T53,T54
110Not Covered
111CoveredT1,T2,T15 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T15
110Not Covered
111CoveredT1,T15,T17
Cond Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Cond Coverage for Module self-instances :
SCORECOND
97.92 91.67
tb.dut.usbdev_rxfifo

SCORECOND
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

TotalCoveredPercent
Conditions161168.75
Logical161168.75
Non-Logical00
Event00

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T15
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T2,T15 

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT1,T2,T15 

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T15
110Not Covered
111CoveredT1,T2,T15 

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT1,T2,T15
1CoveredT1,T2,T3
Branch Coverage for Module : prim_fifo_sync ( parameter Width=5,Pass=0,Depth=4,OutputZeroIfEmpty=0,Secure=0,DepthW=3,gen_normal_fifo.PtrW=2 + Width=5,Pass=0,Depth=8,OutputZeroIfEmpty=0,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 )
Branch Coverage for Module self-instances :
SCOREBRANCH
97.73 100.00
tb.dut.usbdev_avsetupfifo

SCOREBRANCH
97.73 100.00
tb.dut.usbdev_avoutfifo

Line No.TotalCoveredPercent
Branches 5 5 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T15
0 Covered T1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=40,Pass=1,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Line No.TotalCoveredPercent
Branches 9 9 100.00
TERNARY 130 2 2 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 111 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ?

Branches:
-1-StatusTests
1 Covered T1,T17,T18
0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T17,T18 



	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T17,T18
0 Covered T1,T2,T3

Branch Coverage for Module : prim_fifo_sync ( parameter Width=17,Pass=0,Depth=8,OutputZeroIfEmpty=1,Secure=0,DepthW=4,gen_normal_fifo.PtrW=3 + Width=17,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 + Width=5,Pass=0,Depth=1,OutputZeroIfEmpty=1,Secure=0,DepthW=1,gen_normal_fifo.PtrW=1 )
Branch Coverage for Module self-instances :
SCOREBRANCH
97.92 100.00
tb.dut.usbdev_rxfifo

SCOREBRANCH
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

SCOREBRANCH
100.00 100.00
tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Line No.TotalCoveredPercent
Branches 7 7 100.00
TERNARY 138 2 2 100.00
IF 69 3 3 100.00
IF 123 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T15 



	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3 



	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T1,T2,T15
0 Covered T1,T2,T3

Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 6 6 100.00 6 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 6 6 100.00 6 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 2147483647 563916785 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 2147483647 467116607 0 0
gen_passthru_fifo.paramCheckPass 22440 22440 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 563916785 0 0
T1 2299320 732010 0 0
T2 254112 23769 0 0
T3 8459856 736 0 0
T4 0 232082 0 0
T5 0 126765 0 0
T15 146124 7015 0 0
T16 108408 1244 0 0
T17 7663608 430080 0 0
T18 357384 7495 0 0
T19 118968 1187 0 0
T20 388056 29214 0 0
T21 98100 1520 0 0
T22 0 2368 0 0
T28 0 1910 0 0
T38 0 28 0 0
T51 0 66 0 0
T83 0 1636 0 0
T84 0 84800 0 0
T85 0 112732 0 0
T86 0 80 0 0
T87 0 24960 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 2299320 2298720 0 0
T2 254112 253512 0 0
T3 8459856 8459184 0 0
T15 146124 145308 0 0
T16 108408 107220 0 0
T17 7663608 7662444 0 0
T18 357384 356280 0 0
T19 118968 117900 0 0
T20 388056 387036 0 0
T21 98100 97104 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 2299320 2298720 0 0
T2 254112 253512 0 0
T3 8459856 8459184 0 0
T15 146124 145308 0 0
T16 108408 107220 0 0
T17 7663608 7662444 0 0
T18 357384 356280 0 0
T19 118968 117900 0 0
T20 388056 387036 0 0
T21 98100 97104 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 2299320 2298720 0 0
T2 254112 253512 0 0
T3 8459856 8459184 0 0
T15 146124 145308 0 0
T16 108408 107220 0 0
T17 7663608 7662444 0 0
T18 357384 356280 0 0
T19 118968 117900 0 0
T20 388056 387036 0 0
T21 98100 97104 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 467116607 0 0
T1 1149660 371458 0 0
T2 127056 22935 0 0
T3 4229928 0 0 0
T4 0 232541 0 0
T5 0 128826 0 0
T15 73062 11488 0 0
T16 54204 1200 0 0
T17 3831804 428092 0 0
T18 178692 7619 0 0
T19 59484 2928 0 0
T20 194028 28770 0 0
T21 49050 1527 0 0
T22 0 5574 0 0
T27 0 2983 0 0
T28 0 1808 0 0
T38 0 28 0 0
T51 0 66 0 0
T83 0 1632 0 0
T84 0 50880 0 0
T85 0 112732 0 0
T86 0 48 0 0
T87 0 24960 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 22440 22440 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T15 6 6 0 0
T16 6 6 0 0
T17 6 6 0 0
T18 6 6 0 0
T19 6 6 0 0
T20 6 6 0 0
T21 6 6 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%