Unified Coverage Report :: Module Instance :: tb.dut.usbdev_avsetupfifo

Module Instance : tb.dut.usbdev_avsetupfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	96.77			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_avoutfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.19	100.00	96.77			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.usbdev_rxfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	98.59	88.57			96.00	100.00	gen_no_stubbed_memory.u_tlul2sram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T15

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T52,T54,T88
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T15

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T15
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T15,T18

---

Branch Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T15
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avsetupfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	591616758	134887732	0	0
DepthKnown_A	591616758	591331147	0	0
RvalidKnown_A	591616758	591331147	0	0
WreadyKnown_A	591616758	591331147	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	591616758	134887732	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	134887732	0	0
T1	191610	185549	0	0
T2	21176	10311	0	0
T3	704988	0	0	0
T4	0	116049	0	0
T5	0	126765	0	0
T15	12177	6517	0	0
T16	9034	0	0	0
T17	638634	0	0	0
T18	29782	1714	0	0
T19	9914	0	0	0
T20	32338	4112	0	0
T21	8175	0	0	0
T28	0	1677	0	0
T83	0	1630	0	0
T85	0	112732	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	134887732	0	0
T1	191610	185549	0	0
T2	21176	10311	0	0
T3	704988	0	0	0
T4	0	116049	0	0
T5	0	126765	0	0
T15	12177	6517	0	0
T16	9034	0	0	0
T17	638634	0	0	0
T18	29782	1714	0	0
T19	9914	0	0	0
T20	32338	4112	0	0
T21	8175	0	0	0
T28	0	1677	0	0
T83	0	1630	0	0
T85	0	112732	0	0

Line Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T16

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T53,T89
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T16

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T16
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T17,T18

---

Branch Coverage for Instance : tb.dut.usbdev_avoutfifo

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_avoutfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	591616758	282632515	0	0
DepthKnown_A	591616758	591331147	0	0
RvalidKnown_A	591616758	591331147	0	0
WreadyKnown_A	591616758	591331147	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	591616758	282632515	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	282632515	0	0
T1	191610	185533	0	0
T2	21176	12564	0	0
T3	704988	0	0	0
T4	0	116033	0	0
T15	12177	0	0	0
T16	9034	1200	0	0
T17	638634	388334	0	0
T18	29782	5137	0	0
T19	9914	1015	0	0
T20	32338	24648	0	0
T21	8175	1409	0	0
T22	0	2368	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	282632515	0	0
T1	191610	185533	0	0
T2	21176	12564	0	0
T3	704988	0	0	0
T4	0	116033	0	0
T15	12177	0	0	0
T16	9034	1200	0	0
T17	638634	388334	0	0
T18	29782	5137	0	0
T19	9914	1015	0	0
T20	32338	24648	0	0
T21	8175	1409	0	0
T22	0	2368	0	0

Line Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T42,T43
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T15,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T15,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Not Covered
1	0	1	Covered	T1,T15,T17
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T15,T17

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.usbdev_rxfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T15,T17

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T15,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.usbdev_rxfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	591616758	45975406	0	0
DepthKnown_A	591616758	591331147	0	0
RvalidKnown_A	591616758	591331147	0	0
WreadyKnown_A	591616758	591331147	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	591616758	45975406	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	45975406	0	0
T1	191610	340	0	0
T2	21176	0	0	0
T3	704988	0	0	0
T4	0	459	0	0
T5	0	2061	0	0
T15	12177	4971	0	0
T16	9034	0	0	0
T17	638634	26392	0	0
T18	29782	620	0	0
T19	9914	1913	0	0
T20	32338	0	0	0
T21	8175	91	0	0
T22	0	3206	0	0
T27	0	2983	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	45975406	0	0
T1	191610	340	0	0
T2	21176	0	0	0
T3	704988	0	0	0
T4	0	459	0	0
T5	0	2061	0	0
T15	12177	4971	0	0
T16	9034	0	0	0
T17	638634	26392	0	0
T18	29782	620	0	0
T19	9914	1913	0	0
T20	32338	0	0	0
T21	8175	91	0	0
T22	0	3206	0	0
T27	0	2983	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	593504361	20153924	0	0
DepthKnown_A	593504361	593177268	0	0
RvalidKnown_A	593504361	593177268	0	0
WreadyKnown_A	593504361	593177268	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	20153924	0	0
T1	191610	90223	0	0
T2	21176	69	0	0
T3	704988	184	0	0
T15	12177	48	0	0
T16	9034	11	0	0
T17	638634	7182	0	0
T18	29782	124	0	0
T19	9914	16	0	0
T20	32338	60	0	0
T21	8175	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	593504361	28278023	0	0
DepthKnown_A	593504361	593177268	0	0
RvalidKnown_A	593504361	593177268	0	0
WreadyKnown_A	593504361	593177268	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	28278023	0	0
T1	191610	90223	0	0
T2	21176	348	0	0
T3	704988	184	0	0
T15	12177	201	0	0
T16	9034	11	0	0
T17	638634	7066	0	0
T18	29782	124	0	0
T19	9914	70	0	0
T20	32338	162	0	0
T21	8175	21	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	593504361	955703	0	0
DepthKnown_A	593504361	593177268	0	0
RvalidKnown_A	593504361	593177268	0	0
WreadyKnown_A	593504361	593177268	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	955703	0	0
T1	191610	18	0	0
T2	21176	12	0	0
T3	704988	0	0	0
T15	12177	0	0	0
T16	9034	0	0	0
T17	638634	5958	0	0
T18	29782	68	0	0
T19	9914	0	0	0
T20	32338	8	0	0
T21	8175	9	0	0
T28	0	51	0	0
T83	0	2	0	0
T84	0	16960	0	0
T86	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	593504361	1889626	0	0
DepthKnown_A	593504361	593177268	0	0
RvalidKnown_A	593504361	593177268	0	0
WreadyKnown_A	593504361	593177268	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	1889626	0	0
T1	191610	18	0	0
T2	21176	60	0	0
T3	704988	0	0	0
T15	12177	0	0	0
T16	9034	0	0	0
T17	638634	5958	0	0
T18	29782	68	0	0
T19	9914	0	0	0
T20	32338	10	0	0
T21	8175	9	0	0
T28	0	51	0	0
T83	0	2	0	0
T84	0	16960	0	0
T86	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	593504361	19134505	0	0
DepthKnown_A	593504361	593177268	0	0
RvalidKnown_A	593504361	593177268	0	0
WreadyKnown_A	593504361	593177268	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	19134505	0	0
T1	191610	90205	0	0
T2	21176	57	0	0
T3	704988	184	0	0
T15	12177	48	0	0
T16	9034	11	0	0
T17	638634	1108	0	0
T18	29782	56	0	0
T19	9914	16	0	0
T20	32338	52	0	0
T21	8175	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	593504361	26388397	0	0
DepthKnown_A	593504361	593177268	0	0
RvalidKnown_A	593504361	593177268	0	0
WreadyKnown_A	593504361	593177268	0	0
gen_passthru_fifo.paramCheckPass	3740	3740	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	26388397	0	0
T1	191610	90205	0	0
T2	21176	288	0	0
T3	704988	184	0	0
T15	12177	201	0	0
T16	9034	11	0	0
T17	638634	1108	0	0
T18	29782	56	0	0
T19	9914	70	0	0
T20	32338	152	0	0
T21	8175	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	593504361	593177268	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	3740	3740	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T15	1	1	0	0
T16	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0
T21	1	1	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Covered	Percent
Conditions	11	11	100.00
Logical	11	11	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T17
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T2,T17

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T17

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T2,T17,T18
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T2,T17

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T17

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T17
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	591616758	1818091	0	0
DepthKnown_A	591616758	591331147	0	0
RvalidKnown_A	591616758	591331147	0	0
WreadyKnown_A	591616758	591331147	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	591616758	1818091	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	1818091	0	0
T1	191610	18	0	0
T2	21176	60	0	0
T3	704988	0	0	0
T15	12177	0	0	0
T16	9034	0	0	0
T17	638634	5958	0	0
T18	29782	68	0	0
T19	9914	0	0	0
T20	32338	10	0	0
T21	8175	9	0	0
T28	0	51	0	0
T83	0	2	0	0
T84	0	16960	0	0
T86	0	16	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	1818091	0	0
T1	191610	18	0	0
T2	21176	60	0	0
T3	704988	0	0	0
T15	12177	0	0	0
T16	9034	0	0	0
T17	638634	5958	0	0
T18	29782	68	0	0
T19	9914	0	0	0
T20	32338	10	0	0
T21	8175	9	0	0
T28	0	51	0	0
T83	0	2	0	0
T84	0	16960	0	0
T86	0	16	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Covered	Percent
Conditions	10	10	100.00
Logical	10	10	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T17,T18
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T17,T18

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T17,T18

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T17,T18

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T17,T18
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T17,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T17,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	591616758	615105	0	0
DepthKnown_A	591616758	591331147	0	0
RvalidKnown_A	591616758	591331147	0	0
WreadyKnown_A	591616758	591331147	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	591616758	615105	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	615105	0	0
T1	191610	9	0	0
T2	21176	0	0	0
T3	704988	0	0	0
T15	12177	0	0	0
T16	9034	0	0	0
T17	638634	3704	0	0
T18	29782	40	0	0
T19	9914	0	0	0
T20	32338	0	0	0
T21	8175	9	0	0
T28	0	40	0	0
T38	0	14	0	0
T51	0	33	0	0
T84	0	16960	0	0
T86	0	16	0	0
T87	0	12480	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	615105	0	0
T1	191610	9	0	0
T2	21176	0	0	0
T3	704988	0	0	0
T15	12177	0	0	0
T16	9034	0	0	0
T17	638634	3704	0	0
T18	29782	40	0	0
T19	9914	0	0	0
T20	32338	0	0	0
T21	8175	9	0	0
T28	0	40	0	0
T38	0	14	0	0
T51	0	33	0	0
T84	0	16960	0	0
T86	0	16	0	0
T87	0	12480	0	0

Line Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
108	1	1
111	1	1
112	1	1
			MISSING_ELSE
116	1	1
130	1	1
131	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Covered	Percent
Conditions	18	18	100.00
Logical	18	18	100.00
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T36,T81,T82
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Covered	T1,T2,T3
1	0	Excluded		VC_COV_UNR
1	1	Covered	T1,T17,T18

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T17,T18

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Covered	T17,T18,T21
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T1,T17,T18

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T17,T18

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T17,T18

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T36,T81,T82
1	0	Covered	T1,T17,T18
1	1	Covered	T1,T2,T3

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (40'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T1,T17,T18
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Line No.	Total	Covered	Percent
Branches		9	9	100.00
TERNARY	130	2	2	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	130	((gen_normal_fifo.fifo_empty && wvalid_i)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T17,T18
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T17,T18

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T17,T18
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_no_stubbed_memory.u_tlul2sram.u_rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	591616758	1187758	0	0
DepthKnown_A	591616758	591331147	0	0
RvalidKnown_A	591616758	591331147	0	0
WreadyKnown_A	591616758	591331147	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	591616758	1187758	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	1187758	0	0
T1	191610	9	0	0
T2	21176	0	0	0
T3	704988	0	0	0
T15	12177	0	0	0
T16	9034	0	0	0
T17	638634	3704	0	0
T18	29782	40	0	0
T19	9914	0	0	0
T20	32338	0	0	0
T21	8175	9	0	0
T28	0	40	0	0
T38	0	14	0	0
T51	0	33	0	0
T84	0	16960	0	0
T86	0	16	0	0
T87	0	12480	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	591331147	0	0
T1	191610	191560	0	0
T2	21176	21126	0	0
T3	704988	704932	0	0
T15	12177	12109	0	0
T16	9034	8935	0	0
T17	638634	638537	0	0
T18	29782	29690	0	0
T19	9914	9825	0	0
T20	32338	32253	0	0
T21	8175	8092	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	591616758	1187758	0	0
T1	191610	9	0	0
T2	21176	0	0	0
T3	704988	0	0	0
T15	12177	0	0	0
T16	9034	0	0	0
T17	638634	3704	0	0
T18	29782	40	0	0
T19	9914	0	0	0
T20	32338	0	0	0
T21	8175	9	0	0
T28	0	40	0	0
T38	0	14	0	0
T51	0	33	0	0
T84	0	16960	0	0
T86	0	16	0	0
T87	0	12480	0	0