Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	0	72	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	72	0	72	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	368	1			T1	8		T9	5		T6	2
all_values[1]	368	1			T1	8		T9	5		T6	2
all_values[2]	368	1			T1	8		T9	5		T6	2
all_values[3]	368	1			T1	8		T9	5		T6	2
all_values[4]	368	1			T1	8		T9	5		T6	2
all_values[5]	368	1			T1	8		T9	5		T6	2
all_values[6]	368	1			T1	8		T9	5		T6	2
all_values[7]	368	1			T1	8		T9	5		T6	2
all_values[8]	368	1			T1	8		T9	5		T6	2
all_values[9]	368	1			T1	8		T9	5		T6	2
all_values[10]	368	1			T1	8		T9	5		T6	2
all_values[11]	368	1			T1	8		T9	5		T6	2
all_values[12]	368	1			T1	8		T9	5		T6	2
all_values[13]	368	1			T1	8		T9	5		T6	2
all_values[14]	368	1			T1	8		T9	5		T6	2
all_values[15]	368	1			T1	8		T9	5		T6	2
all_values[16]	368	1			T1	8		T9	5		T6	2
all_values[17]	368	1			T1	8		T9	5		T6	2

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

8868

1

T1

189

T9

108

T6

64

auto[1]

2908

1

T1

67

T9

52

T18

36

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

9476

1

T1

211

T9

118

T6

63

auto[1]

2300

1

T1

45

T9

42

T6

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	0	72	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	144	1			T1	4		T6	2		T8	2
all_values[0]	auto[0]	auto[1]	59	1			T1	2		T18	1		T19	2
all_values[0]	auto[1]	auto[0]	98	1			T9	2		T19	3		T20	1
all_values[0]	auto[1]	auto[1]	67	1			T1	2		T9	3		T18	1
all_values[1]	auto[0]	auto[0]	153	1			T1	5		T6	2		T8	2
all_values[1]	auto[0]	auto[1]	61	1			T1	1		T9	2		T19	1
all_values[1]	auto[1]	auto[0]	103	1			T1	1		T9	2		T18	2
all_values[1]	auto[1]	auto[1]	51	1			T1	1		T9	1		T18	2
all_values[2]	auto[0]	auto[0]	106	1			T1	2		T9	1		T6	1
all_values[2]	auto[0]	auto[1]	77	1			T1	1		T9	2		T6	1
all_values[2]	auto[1]	auto[0]	105	1			T1	4		T9	1		T18	1
all_values[2]	auto[1]	auto[1]	80	1			T1	1		T9	1		T18	4
all_values[3]	auto[0]	auto[0]	112	1			T1	3		T9	1		T6	2
all_values[3]	auto[0]	auto[1]	71	1			T1	1		T18	1		T19	1
all_values[3]	auto[1]	auto[0]	105	1			T1	2		T9	1		T18	1
all_values[3]	auto[1]	auto[1]	80	1			T1	2		T9	3		T18	2
all_values[4]	auto[0]	auto[0]	148	1			T1	4		T9	1		T6	2
all_values[4]	auto[0]	auto[1]	54	1			T1	2		T19	1		T20	3
all_values[4]	auto[1]	auto[0]	104	1			T1	1		T9	2		T18	3
all_values[4]	auto[1]	auto[1]	62	1			T1	1		T9	2		T18	2
all_values[5]	auto[0]	auto[0]	165	1			T1	5		T6	2		T8	2
all_values[5]	auto[0]	auto[1]	62	1			T9	1		T18	3		T19	4
all_values[5]	auto[1]	auto[0]	82	1			T1	1		T9	2		T18	1
all_values[5]	auto[1]	auto[1]	59	1			T1	2		T9	2		T20	1
all_values[6]	auto[0]	auto[0]	131	1			T1	4		T9	3		T6	2
all_values[6]	auto[0]	auto[1]	61	1			T1	3		T9	1		T18	1
all_values[6]	auto[1]	auto[0]	114	1			T1	1		T19	5		T20	2
all_values[6]	auto[1]	auto[1]	62	1			T9	1		T20	1		T21	1
all_values[7]	auto[0]	auto[0]	152	1			T9	1		T6	2		T8	2
all_values[7]	auto[0]	auto[1]	58	1			T1	2		T18	1		T19	2
all_values[7]	auto[1]	auto[0]	97	1			T1	4		T9	4		T18	2
all_values[7]	auto[1]	auto[1]	61	1			T1	2		T18	1		T20	1
all_values[8]	auto[0]	auto[0]	162	1			T1	3		T9	2		T6	2
all_values[8]	auto[0]	auto[1]	55	1			T18	1		T19	1		T20	2
all_values[8]	auto[1]	auto[0]	102	1			T1	5		T9	3		T18	1
all_values[8]	auto[1]	auto[1]	49	1			T18	1		T19	1		T20	2
all_values[9]	auto[0]	auto[0]	153	1			T1	7		T9	3		T6	2
all_values[9]	auto[0]	auto[1]	63	1			T9	1		T19	1		T20	1
all_values[9]	auto[1]	auto[0]	100	1			T1	1		T19	2		T20	1
all_values[9]	auto[1]	auto[1]	52	1			T9	1		T18	2		T19	4
all_values[10]	auto[0]	auto[0]	149	1			T9	1		T6	2		T8	2
all_values[10]	auto[0]	auto[1]	62	1			T1	3		T18	2		T19	2
all_values[10]	auto[1]	auto[0]	85	1			T1	2		T9	2		T19	2
all_values[10]	auto[1]	auto[1]	72	1			T1	3		T9	2		T18	1
all_values[11]	auto[0]	auto[0]	155	1			T1	5		T9	1		T6	2
all_values[11]	auto[0]	auto[1]	71	1			T1	1		T9	4		T18	4
all_values[11]	auto[1]	auto[0]	84	1			T1	2		T19	2		T20	3
all_values[11]	auto[1]	auto[1]	58	1			T19	1		T20	2		T21	1
all_values[12]	auto[0]	auto[0]	128	1			T1	1		T9	1		T6	2
all_values[12]	auto[0]	auto[1]	69	1			T1	1		T9	3		T19	2
all_values[12]	auto[1]	auto[0]	99	1			T1	6		T18	3		T19	1
all_values[12]	auto[1]	auto[1]	72	1			T9	1		T18	2		T19	4
all_values[13]	auto[0]	auto[0]	133	1			T1	3		T9	3		T6	2
all_values[13]	auto[0]	auto[1]	68	1			T1	1		T9	1		T18	2
all_values[13]	auto[1]	auto[0]	98	1			T1	3		T19	1		T20	4
all_values[13]	auto[1]	auto[1]	69	1			T1	1		T9	1		T18	1
all_values[14]	auto[0]	auto[0]	158	1			T1	4		T9	1		T6	2
all_values[14]	auto[0]	auto[1]	66	1			T1	2		T9	1		T18	4
all_values[14]	auto[1]	auto[0]	95	1			T1	1		T9	3		T19	1
all_values[14]	auto[1]	auto[1]	49	1			T1	1		T20	1		T21	2
all_values[15]	auto[0]	auto[0]	123	1			T1	1		T6	2		T8	2
all_values[15]	auto[0]	auto[1]	85	1			T9	1		T18	2		T19	4
all_values[15]	auto[1]	auto[0]	84	1			T1	6		T9	1		T20	2
all_values[15]	auto[1]	auto[1]	76	1			T1	1		T9	3		T18	2
all_values[16]	auto[0]	auto[0]	128	1			T9	1		T6	2		T8	2
all_values[16]	auto[0]	auto[1]	72	1			T1	3		T19	4		T20	2
all_values[16]	auto[1]	auto[0]	107	1			T1	3		T9	1		T19	1
all_values[16]	auto[1]	auto[1]	61	1			T1	2		T9	3		T18	1
all_values[17]	auto[0]	auto[0]	149	1			T1	2		T6	2		T8	2
all_values[17]	auto[0]	auto[1]	53	1			T1	1		T9	1		T20	2
all_values[17]	auto[1]	auto[0]	113	1			T1	3		T9	4		T19	3
all_values[17]	auto[1]	auto[1]	53	1			T1	2		T19	3		T21	1