Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
61.28 65.59 60.85 86.35 0.00 71.17 97.77 47.24


Total tests in report: 175
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
53.33 53.33 65.06 65.06 56.71 56.71 84.51 84.51 0.00 0.00 70.55 70.55 91.62 91.62 4.89 4.89 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3137277217
57.41 4.07 65.06 0.00 57.43 0.71 87.79 3.29 0.00 0.00 70.55 0.00 91.62 0.00 29.41 24.52 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1155279628
60.51 3.10 65.27 0.21 59.26 1.83 91.31 3.52 0.00 0.00 70.80 0.25 97.21 5.59 39.73 10.32 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3542680103
61.20 0.69 65.31 0.04 59.54 0.29 94.48 3.17 0.00 0.00 70.88 0.08 97.21 0.00 41.00 1.27 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.204118487
61.75 0.55 65.31 0.00 59.54 0.00 94.72 0.23 0.00 0.00 70.88 0.00 97.49 0.28 44.34 3.35 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.16660329
61.98 0.23 65.31 0.00 59.76 0.21 94.84 0.12 0.00 0.00 70.88 0.00 97.49 0.00 45.61 1.27 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3771982316
62.12 0.14 65.31 0.00 60.61 0.86 94.84 0.00 0.00 0.00 70.88 0.00 97.49 0.00 45.70 0.09 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3197630464
62.25 0.13 65.31 0.00 60.61 0.00 94.84 0.00 0.00 0.00 70.88 0.00 97.49 0.00 46.61 0.90 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2307051348
62.34 0.10 65.40 0.09 60.66 0.05 95.07 0.23 0.00 0.00 71.17 0.29 97.49 0.00 46.61 0.00 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2253432929
62.40 0.05 65.40 0.00 60.76 0.10 95.07 0.00 0.00 0.00 71.17 0.00 97.77 0.28 46.61 0.00 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2283824952
62.44 0.04 65.40 0.00 60.76 0.00 95.07 0.00 0.00 0.00 71.17 0.00 97.77 0.00 46.88 0.27 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.318971223
62.47 0.03 65.59 0.19 60.80 0.05 95.07 0.00 0.00 0.00 71.17 0.00 97.77 0.00 46.88 0.00 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2630123608
62.49 0.03 65.59 0.00 60.80 0.00 95.07 0.00 0.00 0.00 71.17 0.00 97.77 0.00 47.06 0.18 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1647478218
62.52 0.03 65.59 0.00 60.80 0.00 95.07 0.00 0.00 0.00 71.17 0.00 97.77 0.00 47.24 0.18 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2008800887
62.53 0.01 65.59 0.00 60.85 0.05 95.07 0.00 0.00 0.00 71.17 0.00 97.77 0.00 47.24 0.00 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.4134561058

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1684203791
/workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1666274878
/workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1127533417
/workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1533738027
/workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3541292343
/workspace/coverage/cover_reg_top/0.usbdev_intr_test.1571176770
/workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.624653298
/workspace/coverage/cover_reg_top/0.usbdev_mem_walk.816487076
/workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1263527510
/workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.453450636
/workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3277089143
/workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.813788252
/workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2927914550
/workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3333187189
/workspace/coverage/cover_reg_top/1.usbdev_csr_rw.486417086
/workspace/coverage/cover_reg_top/1.usbdev_intr_test.1985433532
/workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2596693093
/workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1375354641
/workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2349083681
/workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3303454233
/workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1430358892
/workspace/coverage/cover_reg_top/10.usbdev_intr_test.1346638918
/workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2987348672
/workspace/coverage/cover_reg_top/10.usbdev_tl_errors.99762598
/workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2190968906
/workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1854574442
/workspace/coverage/cover_reg_top/11.usbdev_intr_test.3591848481
/workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3652097602
/workspace/coverage/cover_reg_top/11.usbdev_tl_errors.245377399
/workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1511396155
/workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3903815210
/workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3561176505
/workspace/coverage/cover_reg_top/12.usbdev_intr_test.1210542624
/workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.764653104
/workspace/coverage/cover_reg_top/12.usbdev_tl_errors.262366579
/workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.465582330
/workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3598768661
/workspace/coverage/cover_reg_top/13.usbdev_intr_test.3596076808
/workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.449869252
/workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4025063957
/workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4208672490
/workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3519899131
/workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1207750321
/workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1837601424
/workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3490847531
/workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3739569873
/workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1060149729
/workspace/coverage/cover_reg_top/15.usbdev_intr_test.2834241883
/workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3347819048
/workspace/coverage/cover_reg_top/15.usbdev_tl_errors.412575328
/workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1171136882
/workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3234645543
/workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2625298145
/workspace/coverage/cover_reg_top/16.usbdev_intr_test.1743619363
/workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1399278400
/workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2389009553
/workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.204102672
/workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2563053204
/workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2576934114
/workspace/coverage/cover_reg_top/17.usbdev_intr_test.1589650799
/workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3855708487
/workspace/coverage/cover_reg_top/17.usbdev_tl_errors.435264964
/workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2788071724
/workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3288604362
/workspace/coverage/cover_reg_top/18.usbdev_intr_test.2422297406
/workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.435776299
/workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1044853909
/workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3692063378
/workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.967705795
/workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1176411643
/workspace/coverage/cover_reg_top/19.usbdev_intr_test.2140994926
/workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3562352640
/workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1309708914
/workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1371181154
/workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1887723542
/workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3380712390
/workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2998997853
/workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3331565812
/workspace/coverage/cover_reg_top/2.usbdev_intr_test.2176451112
/workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2731937432
/workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3531398857
/workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.237979052
/workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3600717465
/workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1081796443
/workspace/coverage/cover_reg_top/20.usbdev_intr_test.1624875564
/workspace/coverage/cover_reg_top/21.usbdev_intr_test.1207425116
/workspace/coverage/cover_reg_top/23.usbdev_intr_test.299229019
/workspace/coverage/cover_reg_top/24.usbdev_intr_test.767417185
/workspace/coverage/cover_reg_top/25.usbdev_intr_test.213439834
/workspace/coverage/cover_reg_top/26.usbdev_intr_test.628303982
/workspace/coverage/cover_reg_top/27.usbdev_intr_test.1834711813
/workspace/coverage/cover_reg_top/28.usbdev_intr_test.1655843611
/workspace/coverage/cover_reg_top/29.usbdev_intr_test.4037961089
/workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3437763455
/workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1717479145
/workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2980691570
/workspace/coverage/cover_reg_top/3.usbdev_csr_rw.752115470
/workspace/coverage/cover_reg_top/3.usbdev_intr_test.2062166605
/workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.450141693
/workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2447529157
/workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1329137697
/workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3952188026
/workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1177271845
/workspace/coverage/cover_reg_top/30.usbdev_intr_test.3005375648
/workspace/coverage/cover_reg_top/31.usbdev_intr_test.2118067419
/workspace/coverage/cover_reg_top/33.usbdev_intr_test.8717864
/workspace/coverage/cover_reg_top/34.usbdev_intr_test.2927927293
/workspace/coverage/cover_reg_top/35.usbdev_intr_test.25172970
/workspace/coverage/cover_reg_top/36.usbdev_intr_test.2245332529
/workspace/coverage/cover_reg_top/37.usbdev_intr_test.3647237122
/workspace/coverage/cover_reg_top/38.usbdev_intr_test.754769174
/workspace/coverage/cover_reg_top/39.usbdev_intr_test.1885693697
/workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.156569462
/workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1371837633
/workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.246655887
/workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1588367608
/workspace/coverage/cover_reg_top/4.usbdev_intr_test.3006795461
/workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4223941855
/workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1971218657
/workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.29248184
/workspace/coverage/cover_reg_top/4.usbdev_tl_errors.702429222
/workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3778489803
/workspace/coverage/cover_reg_top/40.usbdev_intr_test.2094190990
/workspace/coverage/cover_reg_top/41.usbdev_intr_test.1438311693
/workspace/coverage/cover_reg_top/43.usbdev_intr_test.3585255110
/workspace/coverage/cover_reg_top/44.usbdev_intr_test.2833272501
/workspace/coverage/cover_reg_top/45.usbdev_intr_test.2559629416
/workspace/coverage/cover_reg_top/46.usbdev_intr_test.1324252551
/workspace/coverage/cover_reg_top/47.usbdev_intr_test.859286516
/workspace/coverage/cover_reg_top/48.usbdev_intr_test.2251138568
/workspace/coverage/cover_reg_top/49.usbdev_intr_test.1664700324
/workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2822045864
/workspace/coverage/cover_reg_top/5.usbdev_csr_rw.363339130
/workspace/coverage/cover_reg_top/5.usbdev_intr_test.976496655
/workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.155139318
/workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2158318472
/workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3385781431
/workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3783281334
/workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3665588728
/workspace/coverage/cover_reg_top/6.usbdev_intr_test.3594134232
/workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3199740823
/workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2568176405
/workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1488567288
/workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1997688265
/workspace/coverage/cover_reg_top/7.usbdev_csr_rw.4062095678
/workspace/coverage/cover_reg_top/7.usbdev_intr_test.3845922670
/workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4112775162
/workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4213604097
/workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1465822676
/workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2640649972
/workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1681923848
/workspace/coverage/cover_reg_top/8.usbdev_intr_test.183978751
/workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3125810838
/workspace/coverage/cover_reg_top/8.usbdev_tl_errors.946799436
/workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1139267642
/workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.442921198
/workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1169574312
/workspace/coverage/cover_reg_top/9.usbdev_intr_test.4245998571
/workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3721278088
/workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.4192787837



Total test records in report: 175
tests.html | tests1.html | tests2.html
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/cover_reg_top/24.usbdev_intr_test.767417185 Aug 14 04:31:25 PM PDT 24 Aug 14 04:31:26 PM PDT 24 35174723 ps
T2 /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3137277217 Aug 14 04:31:06 PM PDT 24 Aug 14 04:31:07 PM PDT 24 96530403 ps
T3 /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2283824952 Aug 14 04:31:19 PM PDT 24 Aug 14 04:31:25 PM PDT 24 73678874 ps
T9 /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3585255110 Aug 14 04:31:51 PM PDT 24 Aug 14 04:31:52 PM PDT 24 71828318 ps
T6 /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1309708914 Aug 14 04:31:14 PM PDT 24 Aug 14 04:31:16 PM PDT 24 126333385 ps
T7 /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.816487076 Aug 14 04:31:36 PM PDT 24 Aug 14 04:31:39 PM PDT 24 261964983 ps
T10 /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.155139318 Aug 14 04:31:16 PM PDT 24 Aug 14 04:31:17 PM PDT 24 135013375 ps
T8 /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.245377399 Aug 14 04:31:26 PM PDT 24 Aug 14 04:31:29 PM PDT 24 278205281 ps
T4 /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1997688265 Aug 14 04:31:33 PM PDT 24 Aug 14 04:31:35 PM PDT 24 181542721 ps
T18 /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2140994926 Aug 14 04:31:32 PM PDT 24 Aug 14 04:31:33 PM PDT 24 43937273 ps
T5 /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3542680103 Aug 14 04:31:42 PM PDT 24 Aug 14 04:31:49 PM PDT 24 199730689 ps
T19 /workspace/coverage/cover_reg_top/32.usbdev_intr_test.16660329 Aug 14 04:31:49 PM PDT 24 Aug 14 04:31:50 PM PDT 24 43574155 ps
T14 /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.813788252 Aug 14 04:31:16 PM PDT 24 Aug 14 04:31:20 PM PDT 24 524746680 ps
T17 /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3598768661 Aug 14 04:31:37 PM PDT 24 Aug 14 04:31:38 PM PDT 24 69306877 ps
T44 /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.363339130 Aug 14 04:31:31 PM PDT 24 Aug 14 04:31:32 PM PDT 24 53626113 ps
T15 /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3771982316 Aug 14 04:31:19 PM PDT 24 Aug 14 04:31:24 PM PDT 24 1317114576 ps
T30 /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2576934114 Aug 14 04:31:24 PM PDT 24 Aug 14 04:31:25 PM PDT 24 49543221 ps
T20 /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2251138568 Aug 14 04:31:24 PM PDT 24 Aug 14 04:31:25 PM PDT 24 77622641 ps
T21 /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1155279628 Aug 14 04:31:20 PM PDT 24 Aug 14 04:31:21 PM PDT 24 42389471 ps
T45 /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3288604362 Aug 14 04:31:22 PM PDT 24 Aug 14 04:31:24 PM PDT 24 110090385 ps
T22 /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1375354641 Aug 14 04:31:19 PM PDT 24 Aug 14 04:31:21 PM PDT 24 156700572 ps
T62 /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1438311693 Aug 14 04:31:40 PM PDT 24 Aug 14 04:31:41 PM PDT 24 61343729 ps
T16 /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3903815210 Aug 14 04:31:41 PM PDT 24 Aug 14 04:31:44 PM PDT 24 88972523 ps
T31 /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1887723542 Aug 14 04:31:39 PM PDT 24 Aug 14 04:31:45 PM PDT 24 1144596323 ps
T32 /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3437763455 Aug 14 04:30:55 PM PDT 24 Aug 14 04:30:57 PM PDT 24 162499750 ps
T56 /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3647237122 Aug 14 04:31:30 PM PDT 24 Aug 14 04:31:31 PM PDT 24 52978820 ps
T23 /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2731937432 Aug 14 04:31:15 PM PDT 24 Aug 14 04:31:17 PM PDT 24 101375151 ps
T24 /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.465582330 Aug 14 04:31:17 PM PDT 24 Aug 14 04:31:20 PM PDT 24 95140085 ps
T63 /workspace/coverage/cover_reg_top/8.usbdev_intr_test.183978751 Aug 14 04:31:23 PM PDT 24 Aug 14 04:31:24 PM PDT 24 65803676 ps
T46 /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.752115470 Aug 14 04:31:01 PM PDT 24 Aug 14 04:31:02 PM PDT 24 51778693 ps
T33 /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2625298145 Aug 14 04:31:20 PM PDT 24 Aug 14 04:31:21 PM PDT 24 43850693 ps
T34 /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3721278088 Aug 14 04:31:15 PM PDT 24 Aug 14 04:31:16 PM PDT 24 173074343 ps
T57 /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2307051348 Aug 14 04:31:43 PM PDT 24 Aug 14 04:31:44 PM PDT 24 90030756 ps
T58 /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1834711813 Aug 14 04:31:23 PM PDT 24 Aug 14 04:31:24 PM PDT 24 71604990 ps
T59 /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1655843611 Aug 14 04:31:21 PM PDT 24 Aug 14 04:31:22 PM PDT 24 33329878 ps
T25 /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3739569873 Aug 14 04:31:22 PM PDT 24 Aug 14 04:31:24 PM PDT 24 115467393 ps
T47 /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.435776299 Aug 14 04:31:21 PM PDT 24 Aug 14 04:31:22 PM PDT 24 173790043 ps
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T27 /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.204118487 Aug 14 04:32:07 PM PDT 24 Aug 14 04:32:09 PM PDT 24 304582715 ps
T48 /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.318971223 Aug 14 04:31:13 PM PDT 24 Aug 14 04:31:17 PM PDT 24 648569367 ps
T28 /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3197630464 Aug 14 04:30:55 PM PDT 24 Aug 14 04:30:58 PM PDT 24 293218508 ps
T35 /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1176411643 Aug 14 04:31:28 PM PDT 24 Aug 14 04:31:29 PM PDT 24 84977724 ps
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T36 /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3561176505 Aug 14 04:31:31 PM PDT 24 Aug 14 04:31:32 PM PDT 24 67539448 ps
T60 /workspace/coverage/cover_reg_top/26.usbdev_intr_test.628303982 Aug 14 04:31:37 PM PDT 24 Aug 14 04:31:38 PM PDT 24 35921573 ps
T75 /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.4062095678 Aug 14 04:31:30 PM PDT 24 Aug 14 04:31:32 PM PDT 24 70943909 ps
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T64 /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2833272501 Aug 14 04:31:47 PM PDT 24 Aug 14 04:31:48 PM PDT 24 58851695 ps
T77 /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3005375648 Aug 14 04:31:14 PM PDT 24 Aug 14 04:31:15 PM PDT 24 44494014 ps
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T79 /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1571176770 Aug 14 04:30:57 PM PDT 24 Aug 14 04:30:57 PM PDT 24 36973134 ps
T50 /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3952188026 Aug 14 04:31:12 PM PDT 24 Aug 14 04:31:16 PM PDT 24 261149082 ps
T52 /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1329137697 Aug 14 04:31:10 PM PDT 24 Aug 14 04:31:12 PM PDT 24 228942187 ps
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T61 /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2118067419 Aug 14 04:31:19 PM PDT 24 Aug 14 04:31:20 PM PDT 24 31369370 ps
T53 /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2822045864 Aug 14 04:31:34 PM PDT 24 Aug 14 04:31:36 PM PDT 24 182254223 ps
T81 /workspace/coverage/cover_reg_top/23.usbdev_intr_test.299229019 Aug 14 04:31:37 PM PDT 24 Aug 14 04:31:38 PM PDT 24 36713982 ps
T54 /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2788071724 Aug 14 04:31:20 PM PDT 24 Aug 14 04:31:26 PM PDT 24 1494513928 ps
T55 /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.237979052 Aug 14 04:31:12 PM PDT 24 Aug 14 04:31:13 PM PDT 24 111182082 ps
T38 /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2596693093 Aug 14 04:31:20 PM PDT 24 Aug 14 04:31:22 PM PDT 24 83804335 ps
T39 /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3541292343 Aug 14 04:31:16 PM PDT 24 Aug 14 04:31:17 PM PDT 24 87162926 ps
T82 /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.764653104 Aug 14 04:31:18 PM PDT 24 Aug 14 04:31:19 PM PDT 24 112870166 ps
T83 /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1717479145 Aug 14 04:31:15 PM PDT 24 Aug 14 04:31:24 PM PDT 24 1819294586 ps
T40 /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1371837633 Aug 14 04:31:02 PM PDT 24 Aug 14 04:31:07 PM PDT 24 830208298 ps
T84 /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.442921198 Aug 14 04:31:44 PM PDT 24 Aug 14 04:31:46 PM PDT 24 138651300 ps
T85 /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2640649972 Aug 14 04:31:26 PM PDT 24 Aug 14 04:31:28 PM PDT 24 64370860 ps
T51 /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1511396155 Aug 14 04:31:18 PM PDT 24 Aug 14 04:31:22 PM PDT 24 1169990551 ps
T65 /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.204102672 Aug 14 04:31:15 PM PDT 24 Aug 14 04:31:20 PM PDT 24 1229822729 ps
T86 /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2008800887 Aug 14 04:31:31 PM PDT 24 Aug 14 04:31:32 PM PDT 24 42289946 ps
T41 /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.156569462 Aug 14 04:31:12 PM PDT 24 Aug 14 04:31:21 PM PDT 24 357006969 ps
T87 /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.29248184 Aug 14 04:31:13 PM PDT 24 Aug 14 04:31:15 PM PDT 24 96354596 ps
T42 /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.624653298 Aug 14 04:31:21 PM PDT 24 Aug 14 04:31:23 PM PDT 24 82009229 ps
T13 /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3380712390 Aug 14 04:30:50 PM PDT 24 Aug 14 04:30:51 PM PDT 24 152774580 ps
T88 /workspace/coverage/cover_reg_top/9.usbdev_intr_test.4245998571 Aug 14 04:31:17 PM PDT 24 Aug 14 04:31:18 PM PDT 24 42320291 ps
T89 /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2630123608 Aug 14 04:31:19 PM PDT 24 Aug 14 04:31:22 PM PDT 24 247110300 ps
T90 /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2559629416 Aug 14 04:31:24 PM PDT 24 Aug 14 04:31:25 PM PDT 24 61874886 ps
T91 /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2834241883 Aug 14 04:31:10 PM PDT 24 Aug 14 04:31:11 PM PDT 24 37080114 ps
T49 /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2568176405 Aug 14 04:31:18 PM PDT 24 Aug 14 04:31:21 PM PDT 24 238725023 ps
T92 /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2389009553 Aug 14 04:31:17 PM PDT 24 Aug 14 04:31:19 PM PDT 24 222469476 ps
T93 /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3519899131 Aug 14 04:31:20 PM PDT 24 Aug 14 04:31:22 PM PDT 24 189988833 ps
T94 /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2447529157 Aug 14 04:31:17 PM PDT 24 Aug 14 04:31:21 PM PDT 24 161591052 ps
T95 /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3591848481 Aug 14 04:31:13 PM PDT 24 Aug 14 04:31:14 PM PDT 24 37722139 ps
T96 /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1207750321 Aug 14 04:31:23 PM PDT 24 Aug 14 04:31:24 PM PDT 24 146241213 ps
T97 /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1171136882 Aug 14 04:31:17 PM PDT 24 Aug 14 04:31:19 PM PDT 24 283207962 ps
T98 /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.99762598 Aug 14 04:31:22 PM PDT 24 Aug 14 04:31:26 PM PDT 24 117612570 ps
T99 /workspace/coverage/cover_reg_top/38.usbdev_intr_test.754769174 Aug 14 04:31:33 PM PDT 24 Aug 14 04:31:34 PM PDT 24 46370138 ps
T100 /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1210542624 Aug 14 04:31:33 PM PDT 24 Aug 14 04:31:34 PM PDT 24 33162999 ps
T101 /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3594134232 Aug 14 04:31:18 PM PDT 24 Aug 14 04:31:19 PM PDT 24 48927920 ps
T43 /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1681923848 Aug 14 04:31:18 PM PDT 24 Aug 14 04:31:19 PM PDT 24 93092135 ps
T102 /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3385781431 Aug 14 04:31:08 PM PDT 24 Aug 14 04:31:11 PM PDT 24 451006595 ps
T103 /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1624875564 Aug 14 04:31:23 PM PDT 24 Aug 14 04:31:23 PM PDT 24 48010935 ps
T69 /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2190968906 Aug 14 04:31:08 PM PDT 24 Aug 14 04:31:11 PM PDT 24 869079822 ps
T104 /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.412575328 Aug 14 04:31:34 PM PDT 24 Aug 14 04:31:37 PM PDT 24 268476661 ps
T66 /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3778489803 Aug 14 04:31:03 PM PDT 24 Aug 14 04:31:05 PM PDT 24 576666407 ps
T105 /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2245332529 Aug 14 04:31:30 PM PDT 24 Aug 14 04:31:31 PM PDT 24 37089502 ps
T67 /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1177271845 Aug 14 04:31:00 PM PDT 24 Aug 14 04:31:05 PM PDT 24 734916435 ps
T106 /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1207425116 Aug 14 04:31:30 PM PDT 24 Aug 14 04:31:31 PM PDT 24 36608859 ps
T107 /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3331565812 Aug 14 04:31:12 PM PDT 24 Aug 14 04:31:13 PM PDT 24 107132117 ps
T108 /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3783281334 Aug 14 04:31:13 PM PDT 24 Aug 14 04:31:15 PM PDT 24 167838648 ps
T109 /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2158318472 Aug 14 04:31:05 PM PDT 24 Aug 14 04:31:07 PM PDT 24 86545946 ps
T70 /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1139267642 Aug 14 04:31:21 PM PDT 24 Aug 14 04:31:26 PM PDT 24 654019250 ps
T110 /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.4134561058 Aug 14 04:30:53 PM PDT 24 Aug 14 04:30:56 PM PDT 24 316760146 ps
T111 /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1837601424 Aug 14 04:31:23 PM PDT 24 Aug 14 04:31:30 PM PDT 24 76531184 ps
T112 /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3490847531 Aug 14 04:31:18 PM PDT 24 Aug 14 04:31:21 PM PDT 24 256085876 ps
T113 /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.262366579 Aug 14 04:31:15 PM PDT 24 Aug 14 04:31:17 PM PDT 24 115548160 ps
T114 /workspace/coverage/cover_reg_top/35.usbdev_intr_test.25172970 Aug 14 04:31:33 PM PDT 24 Aug 14 04:31:34 PM PDT 24 46180700 ps
T115 /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.4192787837 Aug 14 04:31:21 PM PDT 24 Aug 14 04:31:23 PM PDT 24 339511894 ps
T116 /workspace/coverage/cover_reg_top/47.usbdev_intr_test.859286516 Aug 14 04:31:44 PM PDT 24 Aug 14 04:31:45 PM PDT 24 47888857 ps
T72 /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4208672490 Aug 14 04:31:16 PM PDT 24 Aug 14 04:31:18 PM PDT 24 273922766 ps
T117 /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2349083681 Aug 14 04:31:34 PM PDT 24 Aug 14 04:31:41 PM PDT 24 143394392 ps
T118 /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3652097602 Aug 14 04:31:24 PM PDT 24 Aug 14 04:31:26 PM PDT 24 81965359 ps
T119 /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2176451112 Aug 14 04:31:12 PM PDT 24 Aug 14 04:31:13 PM PDT 24 50127104 ps
T120 /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1885693697 Aug 14 04:31:24 PM PDT 24 Aug 14 04:31:24 PM PDT 24 43738852 ps
T12 /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2253432929 Aug 14 04:31:14 PM PDT 24 Aug 14 04:31:16 PM PDT 24 205267472 ps
T121 /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2987348672 Aug 14 04:31:19 PM PDT 24 Aug 14 04:31:20 PM PDT 24 180062053 ps
T122 /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4213604097 Aug 14 04:31:19 PM PDT 24 Aug 14 04:31:22 PM PDT 24 243729366 ps
T123 /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2927914550 Aug 14 04:31:08 PM PDT 24 Aug 14 04:31:09 PM PDT 24 111129078 ps
T124 /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3855708487 Aug 14 04:31:23 PM PDT 24 Aug 14 04:31:25 PM PDT 24 179045848 ps
T125 /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1985433532 Aug 14 04:30:59 PM PDT 24 Aug 14 04:31:00 PM PDT 24 60839230 ps
T126 /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1060149729 Aug 14 04:31:26 PM PDT 24 Aug 14 04:31:28 PM PDT 24 95047716 ps
T73 /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1081796443 Aug 14 04:31:22 PM PDT 24 Aug 14 04:31:25 PM PDT 24 502456847 ps
T127 /workspace/coverage/cover_reg_top/25.usbdev_intr_test.213439834 Aug 14 04:31:35 PM PDT 24 Aug 14 04:31:36 PM PDT 24 120642731 ps
T128 /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1971218657 Aug 14 04:31:07 PM PDT 24 Aug 14 04:31:12 PM PDT 24 721309409 ps
T129 /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4025063957 Aug 14 04:31:23 PM PDT 24 Aug 14 04:31:26 PM PDT 24 146994148 ps
T130 /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2563053204 Aug 14 04:31:36 PM PDT 24 Aug 14 04:31:38 PM PDT 24 142243334 ps
T131 /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1743619363 Aug 14 04:31:17 PM PDT 24 Aug 14 04:31:18 PM PDT 24 151551211 ps
T132 /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1324252551 Aug 14 04:31:24 PM PDT 24 Aug 14 04:31:25 PM PDT 24 78817280 ps
T133 /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.246655887 Aug 14 04:31:17 PM PDT 24 Aug 14 04:31:19 PM PDT 24 71219672 ps
T134 /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1684203791 Aug 14 04:31:03 PM PDT 24 Aug 14 04:31:07 PM PDT 24 339827756 ps
T135 /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3199740823 Aug 14 04:31:16 PM PDT 24 Aug 14 04:31:17 PM PDT 24 104238196 ps
T136 /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1430358892 Aug 14 04:31:08 PM PDT 24 Aug 14 04:31:09 PM PDT 24 71727640 ps
T137 /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3692063378 Aug 14 04:31:21 PM PDT 24 Aug 14 04:31:24 PM PDT 24 707311667 ps
T138 /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1588367608 Aug 14 04:31:12 PM PDT 24 Aug 14 04:31:13 PM PDT 24 87391100 ps
T139 /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.450141693 Aug 14 04:30:57 PM PDT 24 Aug 14 04:31:00 PM PDT 24 158480971 ps
T140 /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.946799436 Aug 14 04:31:27 PM PDT 24 Aug 14 04:31:28 PM PDT 24 117825682 ps
T68 /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.453450636 Aug 14 04:31:16 PM PDT 24 Aug 14 04:31:21 PM PDT 24 1172664972 ps
T141 /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3600717465 Aug 14 04:31:07 PM PDT 24 Aug 14 04:31:10 PM PDT 24 90286955 ps
T142 /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1854574442 Aug 14 04:31:22 PM PDT 24 Aug 14 04:31:24 PM PDT 24 59854972 ps
T143 /workspace/coverage/cover_reg_top/33.usbdev_intr_test.8717864 Aug 14 04:31:25 PM PDT 24 Aug 14 04:31:25 PM PDT 24 38734719 ps
T144 /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3845922670 Aug 14 04:31:19 PM PDT 24 Aug 14 04:31:20 PM PDT 24 63239836 ps
T145 /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1263527510 Aug 14 04:31:10 PM PDT 24 Aug 14 04:31:11 PM PDT 24 106998767 ps
T146 /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3234645543 Aug 14 04:31:27 PM PDT 24 Aug 14 04:31:29 PM PDT 24 98209133 ps
T147 /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3562352640 Aug 14 04:31:43 PM PDT 24 Aug 14 04:31:45 PM PDT 24 456356521 ps
T148 /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3596076808 Aug 14 04:31:22 PM PDT 24 Aug 14 04:31:23 PM PDT 24 40921259 ps
T149 /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.435264964 Aug 14 04:31:13 PM PDT 24 Aug 14 04:31:14 PM PDT 24 69405788 ps
T150 /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4112775162 Aug 14 04:31:31 PM PDT 24 Aug 14 04:31:35 PM PDT 24 226553551 ps
T151 /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.449869252 Aug 14 04:31:21 PM PDT 24 Aug 14 04:31:22 PM PDT 24 191621471 ps
T152 /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3006795461 Aug 14 04:31:26 PM PDT 24 Aug 14 04:31:26 PM PDT 24 41994545 ps
T71 /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1465822676 Aug 14 04:31:23 PM PDT 24 Aug 14 04:31:28 PM PDT 24 744259861 ps
T153 /workspace/coverage/cover_reg_top/5.usbdev_intr_test.976496655 Aug 14 04:31:11 PM PDT 24 Aug 14 04:31:12 PM PDT 24 53222460 ps
T154 /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2422297406 Aug 14 04:31:19 PM PDT 24 Aug 14 04:31:20 PM PDT 24 39543470 ps
T155 /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1371181154 Aug 14 04:31:19 PM PDT 24 Aug 14 04:31:21 PM PDT 24 79837536 ps
T156 /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2927927293 Aug 14 04:31:40 PM PDT 24 Aug 14 04:31:41 PM PDT 24 41595893 ps
T74 /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1647478218 Aug 14 04:31:16 PM PDT 24 Aug 14 04:31:21 PM PDT 24 875154670 ps
T157 /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.486417086 Aug 14 04:31:21 PM PDT 24 Aug 14 04:31:23 PM PDT 24 68556403 ps
T158 /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2980691570 Aug 14 04:31:21 PM PDT 24 Aug 14 04:31:23 PM PDT 24 126487860 ps
T159 /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3665588728 Aug 14 04:31:19 PM PDT 24 Aug 14 04:31:20 PM PDT 24 69065680 ps
T160 /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1488567288 Aug 14 04:31:14 PM PDT 24 Aug 14 04:31:17 PM PDT 24 445583363 ps
T161 /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.702429222 Aug 14 04:31:19 PM PDT 24 Aug 14 04:31:21 PM PDT 24 69019246 ps
T162 /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2094190990 Aug 14 04:31:26 PM PDT 24 Aug 14 04:31:27 PM PDT 24 61082784 ps
T163 /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3303454233 Aug 14 04:31:18 PM PDT 24 Aug 14 04:31:19 PM PDT 24 99874469 ps
T164 /workspace/coverage/cover_reg_top/29.usbdev_intr_test.4037961089 Aug 14 04:31:23 PM PDT 24 Aug 14 04:31:24 PM PDT 24 68670137 ps
T165 /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1346638918 Aug 14 04:31:25 PM PDT 24 Aug 14 04:31:26 PM PDT 24 72686625 ps
T166 /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3333187189 Aug 14 04:31:20 PM PDT 24 Aug 14 04:31:21 PM PDT 24 90384440 ps
T167 /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4223941855 Aug 14 04:31:12 PM PDT 24 Aug 14 04:31:14 PM PDT 24 118504535 ps
T168 /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1589650799 Aug 14 04:31:25 PM PDT 24 Aug 14 04:31:26 PM PDT 24 44069368 ps
T169 /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1533738027 Aug 14 04:31:12 PM PDT 24 Aug 14 04:31:15 PM PDT 24 101163400 ps
T170 /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3347819048 Aug 14 04:31:23 PM PDT 24 Aug 14 04:31:24 PM PDT 24 205748515 ps
T171 /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1169574312 Aug 14 04:31:13 PM PDT 24 Aug 14 04:31:14 PM PDT 24 59113338 ps
T172 /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3277089143 Aug 14 04:31:07 PM PDT 24 Aug 14 04:31:10 PM PDT 24 130220558 ps
T173 /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2062166605 Aug 14 04:31:29 PM PDT 24 Aug 14 04:31:30 PM PDT 24 36404259 ps
T174 /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1664700324 Aug 14 04:31:22 PM PDT 24 Aug 14 04:31:23 PM PDT 24 42311136 ps
T175 /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3125810838 Aug 14 04:31:20 PM PDT 24 Aug 14 04:31:21 PM PDT 24 144045281 ps

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_hw_reset.3137277217
Short name T2
Test name
Test status
Simulation time 96530403 ps
CPU time 0.81 seconds
Started Aug 14 04:31:06 PM PDT 24
Finished Aug 14 04:31:07 PM PDT 24
Peak memory 206820 kb
Host smart-695ec6cc-0754-4bd7-86c5-1b6318c7269e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3137277217 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_hw_reset.3137277217
Directory /workspace/3.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_intr_test.1155279628
Short name T21
Test name
Test status
Simulation time 42389471 ps
CPU time 0.73 seconds
Started Aug 14 04:31:20 PM PDT 24
Finished Aug 14 04:31:21 PM PDT 24
Peak memory 206648 kb
Host smart-a31058bb-02a5-4098-81cd-ef11ae778bbe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1155279628 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_intr_test.1155279628
Directory /workspace/14.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_mem_rw_with_rand_reset.3542680103
Short name T5
Test name
Test status
Simulation time 199730689 ps
CPU time 1.88 seconds
Started Aug 14 04:31:42 PM PDT 24
Finished Aug 14 04:31:49 PM PDT 24
Peak memory 215400 kb
Host smart-f2d8b20c-427e-4ca1-8524-16035ccec445
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542680103 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbd
ev_csr_mem_rw_with_rand_reset.3542680103
Directory /workspace/18.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_intg_err.204118487
Short name T27
Test name
Test status
Simulation time 304582715 ps
CPU time 2.41 seconds
Started Aug 14 04:32:07 PM PDT 24
Finished Aug 14 04:32:09 PM PDT 24
Peak memory 207132 kb
Host smart-ee6d1306-2897-4235-8208-92e9855eeb0e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=204118487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_intg_err.204118487
Directory /workspace/19.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/32.usbdev_intr_test.16660329
Short name T19
Test name
Test status
Simulation time 43574155 ps
CPU time 0.76 seconds
Started Aug 14 04:31:49 PM PDT 24
Finished Aug 14 04:31:50 PM PDT 24
Peak memory 206800 kb
Host smart-2d70c6ae-f9d2-4f21-a9f0-4bcc9575d617
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=16660329 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.usbdev_intr_test.16660329
Directory /workspace/32.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_intg_err.3771982316
Short name T15
Test name
Test status
Simulation time 1317114576 ps
CPU time 5.13 seconds
Started Aug 14 04:31:19 PM PDT 24
Finished Aug 14 04:31:24 PM PDT 24
Peak memory 207156 kb
Host smart-31041a05-7743-454f-a328-5f6a5cb78e03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3771982316 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_intg_err.3771982316
Directory /workspace/14.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_errors.3197630464
Short name T28
Test name
Test status
Simulation time 293218508 ps
CPU time 3.05 seconds
Started Aug 14 04:30:55 PM PDT 24
Finished Aug 14 04:30:58 PM PDT 24
Peak memory 223040 kb
Host smart-72233047-082e-435a-855c-d7fb9fade9ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3197630464 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_errors.3197630464
Directory /workspace/1.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/42.usbdev_intr_test.2307051348
Short name T57
Test name
Test status
Simulation time 90030756 ps
CPU time 0.8 seconds
Started Aug 14 04:31:43 PM PDT 24
Finished Aug 14 04:31:44 PM PDT 24
Peak memory 206840 kb
Host smart-0e6e4389-fc0e-479a-9bf8-8eeda3ae1d6a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2307051348 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.usbdev_intr_test.2307051348
Directory /workspace/42.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_hw_reset.2253432929
Short name T12
Test name
Test status
Simulation time 205267472 ps
CPU time 1.02 seconds
Started Aug 14 04:31:14 PM PDT 24
Finished Aug 14 04:31:16 PM PDT 24
Peak memory 206820 kb
Host smart-fa7cf555-2e75-4167-a7f9-4f504637e17c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2253432929 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_hw_reset.2253432929
Directory /workspace/4.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_rw.2283824952
Short name T3
Test name
Test status
Simulation time 73678874 ps
CPU time 0.99 seconds
Started Aug 14 04:31:19 PM PDT 24
Finished Aug 14 04:31:25 PM PDT 24
Peak memory 206812 kb
Host smart-4a3910ff-60d7-4f14-9fe9-95afc3e6599a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2283824952 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_csr_rw.2283824952
Directory /workspace/11.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_tl_intg_err.318971223
Short name T48
Test name
Test status
Simulation time 648569367 ps
CPU time 4.29 seconds
Started Aug 14 04:31:13 PM PDT 24
Finished Aug 14 04:31:17 PM PDT 24
Peak memory 207204 kb
Host smart-aad61154-6804-4192-9aa3-679b1d47f2a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=318971223 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_tl_intg_err.318971223
Directory /workspace/1.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_errors.2630123608
Short name T89
Test name
Test status
Simulation time 247110300 ps
CPU time 2.98 seconds
Started Aug 14 04:31:19 PM PDT 24
Finished Aug 14 04:31:22 PM PDT 24
Peak memory 222860 kb
Host smart-f0564d3d-b124-41bf-9bbc-9b857f3c19a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2630123608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_errors.2630123608
Directory /workspace/9.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_intg_err.1647478218
Short name T74
Test name
Test status
Simulation time 875154670 ps
CPU time 4.42 seconds
Started Aug 14 04:31:16 PM PDT 24
Finished Aug 14 04:31:21 PM PDT 24
Peak memory 207216 kb
Host smart-7a338f1d-2e7b-43b6-b7a2-d54ac811fcc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1647478218 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_intg_err.1647478218
Directory /workspace/12.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/22.usbdev_intr_test.2008800887
Short name T86
Test name
Test status
Simulation time 42289946 ps
CPU time 0.73 seconds
Started Aug 14 04:31:31 PM PDT 24
Finished Aug 14 04:31:32 PM PDT 24
Peak memory 206772 kb
Host smart-1fd765a2-7a31-4a91-99c8-e4e629f0ef35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2008800887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.usbdev_intr_test.2008800887
Directory /workspace/22.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_errors.4134561058
Short name T110
Test name
Test status
Simulation time 316760146 ps
CPU time 3.44 seconds
Started Aug 14 04:30:53 PM PDT 24
Finished Aug 14 04:30:56 PM PDT 24
Peak memory 220596 kb
Host smart-d09b034d-a361-424b-8cb9-42b6962003cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4134561058 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_errors.4134561058
Directory /workspace/0.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_aliasing.1684203791
Short name T134
Test name
Test status
Simulation time 339827756 ps
CPU time 3.41 seconds
Started Aug 14 04:31:03 PM PDT 24
Finished Aug 14 04:31:07 PM PDT 24
Peak memory 207108 kb
Host smart-c6d93c50-74e3-42be-a72f-0253a6bcd42a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1684203791 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_aliasing.1684203791
Directory /workspace/0.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_bit_bash.1666274878
Short name T37
Test name
Test status
Simulation time 821605291 ps
CPU time 7.2 seconds
Started Aug 14 04:31:06 PM PDT 24
Finished Aug 14 04:31:13 PM PDT 24
Peak memory 207096 kb
Host smart-51c1db34-1280-43d1-b741-12aec92de142
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1666274878 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_bit_bash.1666274878
Directory /workspace/0.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_hw_reset.1127533417
Short name T11
Test name
Test status
Simulation time 164140802 ps
CPU time 1 seconds
Started Aug 14 04:30:52 PM PDT 24
Finished Aug 14 04:30:54 PM PDT 24
Peak memory 206864 kb
Host smart-896dc954-f262-4e56-8871-d17772dece87
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1127533417 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_hw_reset.1127533417
Directory /workspace/0.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_mem_rw_with_rand_reset.1533738027
Short name T169
Test name
Test status
Simulation time 101163400 ps
CPU time 2.64 seconds
Started Aug 14 04:31:12 PM PDT 24
Finished Aug 14 04:31:15 PM PDT 24
Peak memory 215416 kb
Host smart-840abc74-f657-4fb3-98b6-30e61652c729
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533738027 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbde
v_csr_mem_rw_with_rand_reset.1533738027
Directory /workspace/0.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_csr_rw.3541292343
Short name T39
Test name
Test status
Simulation time 87162926 ps
CPU time 1.04 seconds
Started Aug 14 04:31:16 PM PDT 24
Finished Aug 14 04:31:17 PM PDT 24
Peak memory 206956 kb
Host smart-d43b31d6-69a2-470f-bcfb-c1ebdfee6aa6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3541292343 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_csr_rw.3541292343
Directory /workspace/0.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_intr_test.1571176770
Short name T79
Test name
Test status
Simulation time 36973134 ps
CPU time 0.7 seconds
Started Aug 14 04:30:57 PM PDT 24
Finished Aug 14 04:30:57 PM PDT 24
Peak memory 206868 kb
Host smart-2df86bef-5878-409a-9113-4e01d4203682
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1571176770 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_intr_test.1571176770
Directory /workspace/0.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_partial_access.624653298
Short name T42
Test name
Test status
Simulation time 82009229 ps
CPU time 2.2 seconds
Started Aug 14 04:31:21 PM PDT 24
Finished Aug 14 04:31:23 PM PDT 24
Peak memory 215336 kb
Host smart-ed16d503-fcc6-47e6-87de-9a8e0413a060
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=624653298 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_partial_access.624653298
Directory /workspace/0.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_mem_walk.816487076
Short name T7
Test name
Test status
Simulation time 261964983 ps
CPU time 2.48 seconds
Started Aug 14 04:31:36 PM PDT 24
Finished Aug 14 04:31:39 PM PDT 24
Peak memory 206948 kb
Host smart-2b46774e-1b43-4c2d-9830-2c6d82a42385
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=816487076 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_mem_walk.816487076
Directory /workspace/0.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_same_csr_outstanding.1263527510
Short name T145
Test name
Test status
Simulation time 106998767 ps
CPU time 1.21 seconds
Started Aug 14 04:31:10 PM PDT 24
Finished Aug 14 04:31:11 PM PDT 24
Peak memory 207120 kb
Host smart-f8f5f0b6-bc37-4c93-a746-d8fa7c17d3c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1263527510 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_same_csr_outstanding.1263527510
Directory /workspace/0.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.usbdev_tl_intg_err.453450636
Short name T68
Test name
Test status
Simulation time 1172664972 ps
CPU time 5.14 seconds
Started Aug 14 04:31:16 PM PDT 24
Finished Aug 14 04:31:21 PM PDT 24
Peak memory 207408 kb
Host smart-41499489-6da1-4356-a2ac-7f795918e285
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=453450636 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.usbdev_tl_intg_err.453450636
Directory /workspace/0.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_aliasing.3277089143
Short name T172
Test name
Test status
Simulation time 130220558 ps
CPU time 3.27 seconds
Started Aug 14 04:31:07 PM PDT 24
Finished Aug 14 04:31:10 PM PDT 24
Peak memory 206984 kb
Host smart-91fdfd06-a3f4-4844-a18b-c5edef224ffb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3277089143 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_aliasing.3277089143
Directory /workspace/1.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_bit_bash.813788252
Short name T14
Test name
Test status
Simulation time 524746680 ps
CPU time 4.05 seconds
Started Aug 14 04:31:16 PM PDT 24
Finished Aug 14 04:31:20 PM PDT 24
Peak memory 207108 kb
Host smart-dbb9af6d-e10d-4604-9203-29e7a30840ca
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=813788252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_bit_bash.813788252
Directory /workspace/1.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_hw_reset.2927914550
Short name T123
Test name
Test status
Simulation time 111129078 ps
CPU time 0.82 seconds
Started Aug 14 04:31:08 PM PDT 24
Finished Aug 14 04:31:09 PM PDT 24
Peak memory 206924 kb
Host smart-b9da9ec9-3436-417e-937b-66ed6095e030
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2927914550 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_hw_reset.2927914550
Directory /workspace/1.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_mem_rw_with_rand_reset.3333187189
Short name T166
Test name
Test status
Simulation time 90384440 ps
CPU time 1.25 seconds
Started Aug 14 04:31:20 PM PDT 24
Finished Aug 14 04:31:21 PM PDT 24
Peak memory 215484 kb
Host smart-b56b274c-a7bb-4298-b66a-d9551a20e3c8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333187189 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbde
v_csr_mem_rw_with_rand_reset.3333187189
Directory /workspace/1.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_csr_rw.486417086
Short name T157
Test name
Test status
Simulation time 68556403 ps
CPU time 0.92 seconds
Started Aug 14 04:31:21 PM PDT 24
Finished Aug 14 04:31:23 PM PDT 24
Peak memory 206916 kb
Host smart-759b64cd-e845-4692-9a3d-a5b90055772c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=486417086 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_csr_rw.486417086
Directory /workspace/1.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_intr_test.1985433532
Short name T125
Test name
Test status
Simulation time 60839230 ps
CPU time 0.76 seconds
Started Aug 14 04:30:59 PM PDT 24
Finished Aug 14 04:31:00 PM PDT 24
Peak memory 206836 kb
Host smart-6b83f4f8-41a7-4fb8-85f4-1482a11d7b34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1985433532 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_intr_test.1985433532
Directory /workspace/1.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_partial_access.2596693093
Short name T38
Test name
Test status
Simulation time 83804335 ps
CPU time 2.27 seconds
Started Aug 14 04:31:20 PM PDT 24
Finished Aug 14 04:31:22 PM PDT 24
Peak memory 215312 kb
Host smart-e82b030c-6384-4cdc-9f15-081ec42dc3b8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2596693093 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_partial_access.2596693093
Directory /workspace/1.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_mem_walk.1375354641
Short name T22
Test name
Test status
Simulation time 156700572 ps
CPU time 2.34 seconds
Started Aug 14 04:31:19 PM PDT 24
Finished Aug 14 04:31:21 PM PDT 24
Peak memory 206992 kb
Host smart-072590b0-3224-4426-adac-ffb6c8d7f061
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1375354641 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_mem_walk.1375354641
Directory /workspace/1.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.usbdev_same_csr_outstanding.2349083681
Short name T117
Test name
Test status
Simulation time 143394392 ps
CPU time 1.42 seconds
Started Aug 14 04:31:34 PM PDT 24
Finished Aug 14 04:31:41 PM PDT 24
Peak memory 207172 kb
Host smart-ecdd280c-c32f-40fc-a44b-8edb9a21b434
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2349083681 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.usbdev_same_csr_outstanding.2349083681
Directory /workspace/1.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_mem_rw_with_rand_reset.3303454233
Short name T163
Test name
Test status
Simulation time 99874469 ps
CPU time 1.23 seconds
Started Aug 14 04:31:18 PM PDT 24
Finished Aug 14 04:31:19 PM PDT 24
Peak memory 215372 kb
Host smart-2c6a6eea-7507-44d1-9428-bee741f81789
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303454233 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbd
ev_csr_mem_rw_with_rand_reset.3303454233
Directory /workspace/10.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_csr_rw.1430358892
Short name T136
Test name
Test status
Simulation time 71727640 ps
CPU time 0.82 seconds
Started Aug 14 04:31:08 PM PDT 24
Finished Aug 14 04:31:09 PM PDT 24
Peak memory 206908 kb
Host smart-97f82e5c-5286-4065-9269-16da74af51f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1430358892 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_csr_rw.1430358892
Directory /workspace/10.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_intr_test.1346638918
Short name T165
Test name
Test status
Simulation time 72686625 ps
CPU time 0.71 seconds
Started Aug 14 04:31:25 PM PDT 24
Finished Aug 14 04:31:26 PM PDT 24
Peak memory 206808 kb
Host smart-99b62b36-955a-456f-8303-338275d91c9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1346638918 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_intr_test.1346638918
Directory /workspace/10.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_same_csr_outstanding.2987348672
Short name T121
Test name
Test status
Simulation time 180062053 ps
CPU time 1.2 seconds
Started Aug 14 04:31:19 PM PDT 24
Finished Aug 14 04:31:20 PM PDT 24
Peak memory 207200 kb
Host smart-dac9b4d2-7b86-43bd-a1ca-1a7b8a26d33a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2987348672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_same_csr_outstanding.2987348672
Directory /workspace/10.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_errors.99762598
Short name T98
Test name
Test status
Simulation time 117612570 ps
CPU time 3.34 seconds
Started Aug 14 04:31:22 PM PDT 24
Finished Aug 14 04:31:26 PM PDT 24
Peak memory 221044 kb
Host smart-13630600-713f-4db5-ba57-901f66aacfd6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=99762598 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_errors.99762598
Directory /workspace/10.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.usbdev_tl_intg_err.2190968906
Short name T69
Test name
Test status
Simulation time 869079822 ps
CPU time 3.03 seconds
Started Aug 14 04:31:08 PM PDT 24
Finished Aug 14 04:31:11 PM PDT 24
Peak memory 207136 kb
Host smart-f8a30c8b-23bb-425d-a60a-28979a4ec685
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2190968906 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.usbdev_tl_intg_err.2190968906
Directory /workspace/10.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_csr_mem_rw_with_rand_reset.1854574442
Short name T142
Test name
Test status
Simulation time 59854972 ps
CPU time 1.62 seconds
Started Aug 14 04:31:22 PM PDT 24
Finished Aug 14 04:31:24 PM PDT 24
Peak memory 215348 kb
Host smart-448f7859-1e0d-40e2-adc8-d29ca8d7a598
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854574442 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbd
ev_csr_mem_rw_with_rand_reset.1854574442
Directory /workspace/11.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_intr_test.3591848481
Short name T95
Test name
Test status
Simulation time 37722139 ps
CPU time 0.72 seconds
Started Aug 14 04:31:13 PM PDT 24
Finished Aug 14 04:31:14 PM PDT 24
Peak memory 206812 kb
Host smart-05e6c3bf-f066-405e-baf1-9b127dace73c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3591848481 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_intr_test.3591848481
Directory /workspace/11.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_same_csr_outstanding.3652097602
Short name T118
Test name
Test status
Simulation time 81965359 ps
CPU time 1.6 seconds
Started Aug 14 04:31:24 PM PDT 24
Finished Aug 14 04:31:26 PM PDT 24
Peak memory 207176 kb
Host smart-abe65a43-811a-4c5f-a109-966caba15ffd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3652097602 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_same_csr_outstanding.3652097602
Directory /workspace/11.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_errors.245377399
Short name T8
Test name
Test status
Simulation time 278205281 ps
CPU time 3.28 seconds
Started Aug 14 04:31:26 PM PDT 24
Finished Aug 14 04:31:29 PM PDT 24
Peak memory 207180 kb
Host smart-90d33f2e-3846-4940-b542-fa4d370df133
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=245377399 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_errors.245377399
Directory /workspace/11.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.usbdev_tl_intg_err.1511396155
Short name T51
Test name
Test status
Simulation time 1169990551 ps
CPU time 3.7 seconds
Started Aug 14 04:31:18 PM PDT 24
Finished Aug 14 04:31:22 PM PDT 24
Peak memory 207156 kb
Host smart-bed16522-3206-461a-a04c-d435da6c1b94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1511396155 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.usbdev_tl_intg_err.1511396155
Directory /workspace/11.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_mem_rw_with_rand_reset.3903815210
Short name T16
Test name
Test status
Simulation time 88972523 ps
CPU time 2.17 seconds
Started Aug 14 04:31:41 PM PDT 24
Finished Aug 14 04:31:44 PM PDT 24
Peak memory 215304 kb
Host smart-285bf461-355d-4bf3-b0e5-438b8970f20e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903815210 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbd
ev_csr_mem_rw_with_rand_reset.3903815210
Directory /workspace/12.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_csr_rw.3561176505
Short name T36
Test name
Test status
Simulation time 67539448 ps
CPU time 1 seconds
Started Aug 14 04:31:31 PM PDT 24
Finished Aug 14 04:31:32 PM PDT 24
Peak memory 206924 kb
Host smart-6db6f2a5-8554-4eda-afc0-c9057382b323
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3561176505 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_csr_rw.3561176505
Directory /workspace/12.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_intr_test.1210542624
Short name T100
Test name
Test status
Simulation time 33162999 ps
CPU time 0.69 seconds
Started Aug 14 04:31:33 PM PDT 24
Finished Aug 14 04:31:34 PM PDT 24
Peak memory 206836 kb
Host smart-93dd9bb7-568a-4805-bf01-f6aa9305cfaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1210542624 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_intr_test.1210542624
Directory /workspace/12.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_same_csr_outstanding.764653104
Short name T82
Test name
Test status
Simulation time 112870166 ps
CPU time 1.14 seconds
Started Aug 14 04:31:18 PM PDT 24
Finished Aug 14 04:31:19 PM PDT 24
Peak memory 207128 kb
Host smart-44957c8a-a395-453c-a201-04780ead7be9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=764653104 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_same_csr_outstanding.764653104
Directory /workspace/12.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.usbdev_tl_errors.262366579
Short name T113
Test name
Test status
Simulation time 115548160 ps
CPU time 1.52 seconds
Started Aug 14 04:31:15 PM PDT 24
Finished Aug 14 04:31:17 PM PDT 24
Peak memory 207168 kb
Host smart-30a92bb7-2f95-47fd-8a7b-c6fd20d350a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=262366579 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.usbdev_tl_errors.262366579
Directory /workspace/12.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_mem_rw_with_rand_reset.465582330
Short name T24
Test name
Test status
Simulation time 95140085 ps
CPU time 2.37 seconds
Started Aug 14 04:31:17 PM PDT 24
Finished Aug 14 04:31:20 PM PDT 24
Peak memory 215356 kb
Host smart-fe3b0f0b-30d1-427e-8a87-5bf0091fed73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465582330 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbde
v_csr_mem_rw_with_rand_reset.465582330
Directory /workspace/13.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_csr_rw.3598768661
Short name T17
Test name
Test status
Simulation time 69306877 ps
CPU time 0.92 seconds
Started Aug 14 04:31:37 PM PDT 24
Finished Aug 14 04:31:38 PM PDT 24
Peak memory 206836 kb
Host smart-2eaa0c30-85fa-4772-b128-4525c5a6e792
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3598768661 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_csr_rw.3598768661
Directory /workspace/13.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_intr_test.3596076808
Short name T148
Test name
Test status
Simulation time 40921259 ps
CPU time 0.75 seconds
Started Aug 14 04:31:22 PM PDT 24
Finished Aug 14 04:31:23 PM PDT 24
Peak memory 206836 kb
Host smart-62de2664-dfef-4f52-8823-5ce260e0f446
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3596076808 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_intr_test.3596076808
Directory /workspace/13.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_same_csr_outstanding.449869252
Short name T151
Test name
Test status
Simulation time 191621471 ps
CPU time 1.27 seconds
Started Aug 14 04:31:21 PM PDT 24
Finished Aug 14 04:31:22 PM PDT 24
Peak memory 207204 kb
Host smart-fd6b31d1-28e4-4ffa-be3a-f483808b9bcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=449869252 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_same_csr_outstanding.449869252
Directory /workspace/13.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_errors.4025063957
Short name T129
Test name
Test status
Simulation time 146994148 ps
CPU time 2.02 seconds
Started Aug 14 04:31:23 PM PDT 24
Finished Aug 14 04:31:26 PM PDT 24
Peak memory 207176 kb
Host smart-a100dae2-4300-41cd-9a99-4520160f9032
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4025063957 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_errors.4025063957
Directory /workspace/13.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.usbdev_tl_intg_err.4208672490
Short name T72
Test name
Test status
Simulation time 273922766 ps
CPU time 2.32 seconds
Started Aug 14 04:31:16 PM PDT 24
Finished Aug 14 04:31:18 PM PDT 24
Peak memory 207160 kb
Host smart-b193c9e4-66d2-4ef3-8b9f-8f4336939e15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4208672490 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.usbdev_tl_intg_err.4208672490
Directory /workspace/13.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_mem_rw_with_rand_reset.3519899131
Short name T93
Test name
Test status
Simulation time 189988833 ps
CPU time 1.83 seconds
Started Aug 14 04:31:20 PM PDT 24
Finished Aug 14 04:31:22 PM PDT 24
Peak memory 215188 kb
Host smart-4fe697fb-2c7d-4a4a-a469-def087fbe189
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519899131 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbd
ev_csr_mem_rw_with_rand_reset.3519899131
Directory /workspace/14.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_csr_rw.1207750321
Short name T96
Test name
Test status
Simulation time 146241213 ps
CPU time 0.93 seconds
Started Aug 14 04:31:23 PM PDT 24
Finished Aug 14 04:31:24 PM PDT 24
Peak memory 206768 kb
Host smart-0548f9e1-b65f-47a5-93f9-34760cbd949c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1207750321 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_csr_rw.1207750321
Directory /workspace/14.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_same_csr_outstanding.1837601424
Short name T111
Test name
Test status
Simulation time 76531184 ps
CPU time 1.4 seconds
Started Aug 14 04:31:23 PM PDT 24
Finished Aug 14 04:31:30 PM PDT 24
Peak memory 207208 kb
Host smart-c15dcb25-81a8-45fd-9c8d-bcb05012923d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1837601424 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_same_csr_outstanding.1837601424
Directory /workspace/14.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.usbdev_tl_errors.3490847531
Short name T112
Test name
Test status
Simulation time 256085876 ps
CPU time 2.67 seconds
Started Aug 14 04:31:18 PM PDT 24
Finished Aug 14 04:31:21 PM PDT 24
Peak memory 215344 kb
Host smart-b195bdad-2a5f-4e62-bb33-3dca1df14179
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3490847531 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.usbdev_tl_errors.3490847531
Directory /workspace/14.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_mem_rw_with_rand_reset.3739569873
Short name T25
Test name
Test status
Simulation time 115467393 ps
CPU time 1.25 seconds
Started Aug 14 04:31:22 PM PDT 24
Finished Aug 14 04:31:24 PM PDT 24
Peak memory 217668 kb
Host smart-b175cf06-1208-4ea4-bc02-61e10f73a817
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739569873 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbd
ev_csr_mem_rw_with_rand_reset.3739569873
Directory /workspace/15.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_csr_rw.1060149729
Short name T126
Test name
Test status
Simulation time 95047716 ps
CPU time 1.01 seconds
Started Aug 14 04:31:26 PM PDT 24
Finished Aug 14 04:31:28 PM PDT 24
Peak memory 206708 kb
Host smart-8e18817c-1f5c-4b4b-8e21-ba2e91798a7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1060149729 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_csr_rw.1060149729
Directory /workspace/15.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_intr_test.2834241883
Short name T91
Test name
Test status
Simulation time 37080114 ps
CPU time 0.74 seconds
Started Aug 14 04:31:10 PM PDT 24
Finished Aug 14 04:31:11 PM PDT 24
Peak memory 206776 kb
Host smart-13a63ed6-b02d-44dd-b2e6-290a37cd577f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2834241883 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_intr_test.2834241883
Directory /workspace/15.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_same_csr_outstanding.3347819048
Short name T170
Test name
Test status
Simulation time 205748515 ps
CPU time 1.57 seconds
Started Aug 14 04:31:23 PM PDT 24
Finished Aug 14 04:31:24 PM PDT 24
Peak memory 207116 kb
Host smart-49387896-a653-41d4-a30c-430f51f48939
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3347819048 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_same_csr_outstanding.3347819048
Directory /workspace/15.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_errors.412575328
Short name T104
Test name
Test status
Simulation time 268476661 ps
CPU time 2.79 seconds
Started Aug 14 04:31:34 PM PDT 24
Finished Aug 14 04:31:37 PM PDT 24
Peak memory 223428 kb
Host smart-17818436-74b5-4778-a34f-3093b04a059c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=412575328 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_errors.412575328
Directory /workspace/15.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.usbdev_tl_intg_err.1171136882
Short name T97
Test name
Test status
Simulation time 283207962 ps
CPU time 2.37 seconds
Started Aug 14 04:31:17 PM PDT 24
Finished Aug 14 04:31:19 PM PDT 24
Peak memory 207152 kb
Host smart-340b3bc1-fc79-4011-8a68-4f456f278364
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1171136882 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.usbdev_tl_intg_err.1171136882
Directory /workspace/15.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_mem_rw_with_rand_reset.3234645543
Short name T146
Test name
Test status
Simulation time 98209133 ps
CPU time 1.22 seconds
Started Aug 14 04:31:27 PM PDT 24
Finished Aug 14 04:31:29 PM PDT 24
Peak memory 215452 kb
Host smart-e920dfbd-4996-4caf-912f-670ef360b2a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234645543 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbd
ev_csr_mem_rw_with_rand_reset.3234645543
Directory /workspace/16.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_csr_rw.2625298145
Short name T33
Test name
Test status
Simulation time 43850693 ps
CPU time 0.88 seconds
Started Aug 14 04:31:20 PM PDT 24
Finished Aug 14 04:31:21 PM PDT 24
Peak memory 206828 kb
Host smart-3524b5d4-fa57-4709-9327-d290b22f7c2e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2625298145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_csr_rw.2625298145
Directory /workspace/16.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_intr_test.1743619363
Short name T131
Test name
Test status
Simulation time 151551211 ps
CPU time 0.84 seconds
Started Aug 14 04:31:17 PM PDT 24
Finished Aug 14 04:31:18 PM PDT 24
Peak memory 206876 kb
Host smart-91819cba-fbd1-4bcb-885c-6f26f63d0718
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1743619363 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_intr_test.1743619363
Directory /workspace/16.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_same_csr_outstanding.1399278400
Short name T78
Test name
Test status
Simulation time 64052767 ps
CPU time 0.97 seconds
Started Aug 14 04:31:29 PM PDT 24
Finished Aug 14 04:31:30 PM PDT 24
Peak memory 206908 kb
Host smart-20c86ff8-c876-4bc7-b7f2-6e4f4ea1cb74
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1399278400 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_same_csr_outstanding.1399278400
Directory /workspace/16.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_errors.2389009553
Short name T92
Test name
Test status
Simulation time 222469476 ps
CPU time 2.02 seconds
Started Aug 14 04:31:17 PM PDT 24
Finished Aug 14 04:31:19 PM PDT 24
Peak memory 207168 kb
Host smart-a7796aa2-a5c1-41c3-a9b2-bb187c0a2a49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2389009553 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_errors.2389009553
Directory /workspace/16.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.usbdev_tl_intg_err.204102672
Short name T65
Test name
Test status
Simulation time 1229822729 ps
CPU time 5.32 seconds
Started Aug 14 04:31:15 PM PDT 24
Finished Aug 14 04:31:20 PM PDT 24
Peak memory 207236 kb
Host smart-1f3f817d-ccf6-4530-b173-c51585676b99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=204102672 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.usbdev_tl_intg_err.204102672
Directory /workspace/16.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_mem_rw_with_rand_reset.2563053204
Short name T130
Test name
Test status
Simulation time 142243334 ps
CPU time 1.84 seconds
Started Aug 14 04:31:36 PM PDT 24
Finished Aug 14 04:31:38 PM PDT 24
Peak memory 215404 kb
Host smart-d1d88aa7-7d07-4f0a-b4a1-8adb04f70971
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563053204 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbd
ev_csr_mem_rw_with_rand_reset.2563053204
Directory /workspace/17.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_csr_rw.2576934114
Short name T30
Test name
Test status
Simulation time 49543221 ps
CPU time 0.83 seconds
Started Aug 14 04:31:24 PM PDT 24
Finished Aug 14 04:31:25 PM PDT 24
Peak memory 206892 kb
Host smart-25fdb676-2ab8-419b-a56f-41cbf6aa77c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2576934114 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_csr_rw.2576934114
Directory /workspace/17.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_intr_test.1589650799
Short name T168
Test name
Test status
Simulation time 44069368 ps
CPU time 0.74 seconds
Started Aug 14 04:31:25 PM PDT 24
Finished Aug 14 04:31:26 PM PDT 24
Peak memory 206768 kb
Host smart-87aabba2-8e23-43f3-af2e-bb6c3217bec3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1589650799 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_intr_test.1589650799
Directory /workspace/17.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_same_csr_outstanding.3855708487
Short name T124
Test name
Test status
Simulation time 179045848 ps
CPU time 1.66 seconds
Started Aug 14 04:31:23 PM PDT 24
Finished Aug 14 04:31:25 PM PDT 24
Peak memory 207180 kb
Host smart-ed8988c8-b971-4d57-b63c-f34498bd17e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3855708487 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_same_csr_outstanding.3855708487
Directory /workspace/17.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_errors.435264964
Short name T149
Test name
Test status
Simulation time 69405788 ps
CPU time 1.44 seconds
Started Aug 14 04:31:13 PM PDT 24
Finished Aug 14 04:31:14 PM PDT 24
Peak memory 207228 kb
Host smart-d0dd6ba2-3f6c-4f0d-b4cf-8d3bfbe87d93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=435264964 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_errors.435264964
Directory /workspace/17.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.usbdev_tl_intg_err.2788071724
Short name T54
Test name
Test status
Simulation time 1494513928 ps
CPU time 5.38 seconds
Started Aug 14 04:31:20 PM PDT 24
Finished Aug 14 04:31:26 PM PDT 24
Peak memory 207108 kb
Host smart-ae4a9c1e-1862-41dd-a95e-3221fca0e65d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2788071724 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.usbdev_tl_intg_err.2788071724
Directory /workspace/17.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_csr_rw.3288604362
Short name T45
Test name
Test status
Simulation time 110090385 ps
CPU time 0.97 seconds
Started Aug 14 04:31:22 PM PDT 24
Finished Aug 14 04:31:24 PM PDT 24
Peak memory 206920 kb
Host smart-457b9aa3-aec4-4a79-9026-b0297827adb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3288604362 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_csr_rw.3288604362
Directory /workspace/18.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_intr_test.2422297406
Short name T154
Test name
Test status
Simulation time 39543470 ps
CPU time 0.68 seconds
Started Aug 14 04:31:19 PM PDT 24
Finished Aug 14 04:31:20 PM PDT 24
Peak memory 206820 kb
Host smart-35a7348b-dcdb-4b04-bb29-c4a0c6b129d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2422297406 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_intr_test.2422297406
Directory /workspace/18.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_same_csr_outstanding.435776299
Short name T47
Test name
Test status
Simulation time 173790043 ps
CPU time 1.51 seconds
Started Aug 14 04:31:21 PM PDT 24
Finished Aug 14 04:31:22 PM PDT 24
Peak memory 207196 kb
Host smart-8c8f1f79-8dad-4271-a69a-34161610af2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=435776299 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_same_csr_outstanding.435776299
Directory /workspace/18.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_errors.1044853909
Short name T26
Test name
Test status
Simulation time 411495935 ps
CPU time 3.89 seconds
Started Aug 14 04:31:27 PM PDT 24
Finished Aug 14 04:31:31 PM PDT 24
Peak memory 220480 kb
Host smart-a3ef6f20-a3b4-4b58-ad2b-49e6a413b11e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1044853909 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_errors.1044853909
Directory /workspace/18.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.usbdev_tl_intg_err.3692063378
Short name T137
Test name
Test status
Simulation time 707311667 ps
CPU time 3.06 seconds
Started Aug 14 04:31:21 PM PDT 24
Finished Aug 14 04:31:24 PM PDT 24
Peak memory 207160 kb
Host smart-14dcaaca-9250-4009-99c3-d40da2f95aa3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3692063378 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.usbdev_tl_intg_err.3692063378
Directory /workspace/18.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_mem_rw_with_rand_reset.967705795
Short name T76
Test name
Test status
Simulation time 83999570 ps
CPU time 1.72 seconds
Started Aug 14 04:31:29 PM PDT 24
Finished Aug 14 04:31:31 PM PDT 24
Peak memory 215392 kb
Host smart-393beaf7-ff01-4b10-959b-86f7a6ea3fa5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967705795 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbde
v_csr_mem_rw_with_rand_reset.967705795
Directory /workspace/19.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_csr_rw.1176411643
Short name T35
Test name
Test status
Simulation time 84977724 ps
CPU time 0.87 seconds
Started Aug 14 04:31:28 PM PDT 24
Finished Aug 14 04:31:29 PM PDT 24
Peak memory 206792 kb
Host smart-e5c2c34a-f179-40d0-8f9a-90a3028ee695
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1176411643 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_csr_rw.1176411643
Directory /workspace/19.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_intr_test.2140994926
Short name T18
Test name
Test status
Simulation time 43937273 ps
CPU time 0.69 seconds
Started Aug 14 04:31:32 PM PDT 24
Finished Aug 14 04:31:33 PM PDT 24
Peak memory 206848 kb
Host smart-50440040-9e70-4fbc-a030-395d09f089df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2140994926 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_intr_test.2140994926
Directory /workspace/19.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_same_csr_outstanding.3562352640
Short name T147
Test name
Test status
Simulation time 456356521 ps
CPU time 1.82 seconds
Started Aug 14 04:31:43 PM PDT 24
Finished Aug 14 04:31:45 PM PDT 24
Peak memory 207140 kb
Host smart-437aa407-958b-46b6-93e6-8e5aa4fcca13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3562352640 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_same_csr_outstanding.3562352640
Directory /workspace/19.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.usbdev_tl_errors.1309708914
Short name T6
Test name
Test status
Simulation time 126333385 ps
CPU time 1.5 seconds
Started Aug 14 04:31:14 PM PDT 24
Finished Aug 14 04:31:16 PM PDT 24
Peak memory 207136 kb
Host smart-9f7863e1-b668-4c96-8c6f-f70e33598167
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1309708914 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.usbdev_tl_errors.1309708914
Directory /workspace/19.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_aliasing.1371181154
Short name T155
Test name
Test status
Simulation time 79837536 ps
CPU time 1.81 seconds
Started Aug 14 04:31:19 PM PDT 24
Finished Aug 14 04:31:21 PM PDT 24
Peak memory 207148 kb
Host smart-5560ab1d-a353-4d6f-b896-32af88102d8b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1371181154 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_aliasing.1371181154
Directory /workspace/2.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_bit_bash.1887723542
Short name T31
Test name
Test status
Simulation time 1144596323 ps
CPU time 5.95 seconds
Started Aug 14 04:31:39 PM PDT 24
Finished Aug 14 04:31:45 PM PDT 24
Peak memory 207116 kb
Host smart-5740ff77-bb11-4a79-abe9-4358a0b43fa0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1887723542 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_bit_bash.1887723542
Directory /workspace/2.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_hw_reset.3380712390
Short name T13
Test name
Test status
Simulation time 152774580 ps
CPU time 1.01 seconds
Started Aug 14 04:30:50 PM PDT 24
Finished Aug 14 04:30:51 PM PDT 24
Peak memory 206848 kb
Host smart-e7b4f503-b39d-4331-95b4-c0d3da8717d3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3380712390 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_hw_reset.3380712390
Directory /workspace/2.usbdev_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_mem_rw_with_rand_reset.2998997853
Short name T29
Test name
Test status
Simulation time 162000686 ps
CPU time 1.89 seconds
Started Aug 14 04:31:23 PM PDT 24
Finished Aug 14 04:31:25 PM PDT 24
Peak memory 215472 kb
Host smart-b7e423e7-71a2-421d-8540-d48317d6f87e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998997853 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbde
v_csr_mem_rw_with_rand_reset.2998997853
Directory /workspace/2.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_csr_rw.3331565812
Short name T107
Test name
Test status
Simulation time 107132117 ps
CPU time 0.87 seconds
Started Aug 14 04:31:12 PM PDT 24
Finished Aug 14 04:31:13 PM PDT 24
Peak memory 206924 kb
Host smart-bd593692-59ed-40fb-90f1-5828c9aab509
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3331565812 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_csr_rw.3331565812
Directory /workspace/2.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_intr_test.2176451112
Short name T119
Test name
Test status
Simulation time 50127104 ps
CPU time 0.72 seconds
Started Aug 14 04:31:12 PM PDT 24
Finished Aug 14 04:31:13 PM PDT 24
Peak memory 206808 kb
Host smart-57979189-048f-4e9f-b388-9085037d7d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2176451112 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_intr_test.2176451112
Directory /workspace/2.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_partial_access.2731937432
Short name T23
Test name
Test status
Simulation time 101375151 ps
CPU time 1.4 seconds
Started Aug 14 04:31:15 PM PDT 24
Finished Aug 14 04:31:17 PM PDT 24
Peak memory 215296 kb
Host smart-c778ea24-8f82-4751-bc96-3b6b54a80580
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=2731937432 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_partial_access.2731937432
Directory /workspace/2.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_mem_walk.3531398857
Short name T80
Test name
Test status
Simulation time 525048522 ps
CPU time 4.48 seconds
Started Aug 14 04:30:55 PM PDT 24
Finished Aug 14 04:31:00 PM PDT 24
Peak memory 207020 kb
Host smart-53fa5568-2a47-4442-9949-f0c38b551b19
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3531398857 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_mem_walk.3531398857
Directory /workspace/2.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_same_csr_outstanding.237979052
Short name T55
Test name
Test status
Simulation time 111182082 ps
CPU time 1.16 seconds
Started Aug 14 04:31:12 PM PDT 24
Finished Aug 14 04:31:13 PM PDT 24
Peak memory 207184 kb
Host smart-8e6f4d93-40b2-402a-ba37-bcb6fc850c0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=237979052 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_same_csr_outstanding.237979052
Directory /workspace/2.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_errors.3600717465
Short name T141
Test name
Test status
Simulation time 90286955 ps
CPU time 2.47 seconds
Started Aug 14 04:31:07 PM PDT 24
Finished Aug 14 04:31:10 PM PDT 24
Peak memory 215316 kb
Host smart-05ed93f1-9351-4d28-84ba-3c5c671531ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3600717465 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_errors.3600717465
Directory /workspace/2.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.usbdev_tl_intg_err.1081796443
Short name T73
Test name
Test status
Simulation time 502456847 ps
CPU time 2.82 seconds
Started Aug 14 04:31:22 PM PDT 24
Finished Aug 14 04:31:25 PM PDT 24
Peak memory 207140 kb
Host smart-ae9a6f0b-c162-40cf-bcfb-95f002c4c393
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1081796443 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.usbdev_tl_intg_err.1081796443
Directory /workspace/2.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.usbdev_intr_test.1624875564
Short name T103
Test name
Test status
Simulation time 48010935 ps
CPU time 0.75 seconds
Started Aug 14 04:31:23 PM PDT 24
Finished Aug 14 04:31:23 PM PDT 24
Peak memory 206824 kb
Host smart-ef0acd63-9b54-47f0-90f4-1f43e8dac317
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1624875564 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.usbdev_intr_test.1624875564
Directory /workspace/20.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.usbdev_intr_test.1207425116
Short name T106
Test name
Test status
Simulation time 36608859 ps
CPU time 0.68 seconds
Started Aug 14 04:31:30 PM PDT 24
Finished Aug 14 04:31:31 PM PDT 24
Peak memory 206844 kb
Host smart-631a3988-b9bc-44fc-a710-efa411e0591c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1207425116 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.usbdev_intr_test.1207425116
Directory /workspace/21.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.usbdev_intr_test.299229019
Short name T81
Test name
Test status
Simulation time 36713982 ps
CPU time 0.68 seconds
Started Aug 14 04:31:37 PM PDT 24
Finished Aug 14 04:31:38 PM PDT 24
Peak memory 206812 kb
Host smart-500e927d-6636-48b6-8109-953a51226d40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=299229019 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.usbdev_intr_test.299229019
Directory /workspace/23.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.usbdev_intr_test.767417185
Short name T1
Test name
Test status
Simulation time 35174723 ps
CPU time 0.7 seconds
Started Aug 14 04:31:25 PM PDT 24
Finished Aug 14 04:31:26 PM PDT 24
Peak memory 206756 kb
Host smart-cc45899b-e7c7-425a-b107-20c6d90c27f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=767417185 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.usbdev_intr_test.767417185
Directory /workspace/24.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.usbdev_intr_test.213439834
Short name T127
Test name
Test status
Simulation time 120642731 ps
CPU time 0.8 seconds
Started Aug 14 04:31:35 PM PDT 24
Finished Aug 14 04:31:36 PM PDT 24
Peak memory 206828 kb
Host smart-5b9071bc-49e7-4b5f-96db-03429cd5ded7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=213439834 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.usbdev_intr_test.213439834
Directory /workspace/25.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.usbdev_intr_test.628303982
Short name T60
Test name
Test status
Simulation time 35921573 ps
CPU time 0.69 seconds
Started Aug 14 04:31:37 PM PDT 24
Finished Aug 14 04:31:38 PM PDT 24
Peak memory 206800 kb
Host smart-509c9ed0-a893-480c-8483-fadff7469ab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=628303982 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.usbdev_intr_test.628303982
Directory /workspace/26.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.usbdev_intr_test.1834711813
Short name T58
Test name
Test status
Simulation time 71604990 ps
CPU time 0.74 seconds
Started Aug 14 04:31:23 PM PDT 24
Finished Aug 14 04:31:24 PM PDT 24
Peak memory 206756 kb
Host smart-7b17d79d-e5c9-4b04-adef-f4daf871d612
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1834711813 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.usbdev_intr_test.1834711813
Directory /workspace/27.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.usbdev_intr_test.1655843611
Short name T59
Test name
Test status
Simulation time 33329878 ps
CPU time 0.68 seconds
Started Aug 14 04:31:21 PM PDT 24
Finished Aug 14 04:31:22 PM PDT 24
Peak memory 206816 kb
Host smart-70ecc8bd-cd18-4f47-ae2d-1fadee90b91d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1655843611 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.usbdev_intr_test.1655843611
Directory /workspace/28.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.usbdev_intr_test.4037961089
Short name T164
Test name
Test status
Simulation time 68670137 ps
CPU time 0.75 seconds
Started Aug 14 04:31:23 PM PDT 24
Finished Aug 14 04:31:24 PM PDT 24
Peak memory 206808 kb
Host smart-3a590611-0493-4fd1-9cf8-95b61e10e4b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4037961089 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.usbdev_intr_test.4037961089
Directory /workspace/29.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_aliasing.3437763455
Short name T32
Test name
Test status
Simulation time 162499750 ps
CPU time 1.97 seconds
Started Aug 14 04:30:55 PM PDT 24
Finished Aug 14 04:30:57 PM PDT 24
Peak memory 207072 kb
Host smart-aed27a74-bc2a-43cc-b422-50c0617ead51
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3437763455 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_aliasing.3437763455
Directory /workspace/3.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_bit_bash.1717479145
Short name T83
Test name
Test status
Simulation time 1819294586 ps
CPU time 8.32 seconds
Started Aug 14 04:31:15 PM PDT 24
Finished Aug 14 04:31:24 PM PDT 24
Peak memory 207096 kb
Host smart-ff79f877-636f-4b6c-94a1-1a590c46b50b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1717479145 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_bit_bash.1717479145
Directory /workspace/3.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_mem_rw_with_rand_reset.2980691570
Short name T158
Test name
Test status
Simulation time 126487860 ps
CPU time 1.32 seconds
Started Aug 14 04:31:21 PM PDT 24
Finished Aug 14 04:31:23 PM PDT 24
Peak memory 215364 kb
Host smart-7cadc407-44ff-4a97-befa-d45a81e920a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980691570 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbde
v_csr_mem_rw_with_rand_reset.2980691570
Directory /workspace/3.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_csr_rw.752115470
Short name T46
Test name
Test status
Simulation time 51778693 ps
CPU time 0.83 seconds
Started Aug 14 04:31:01 PM PDT 24
Finished Aug 14 04:31:02 PM PDT 24
Peak memory 206936 kb
Host smart-bc559da5-58d7-43eb-b660-21505ce4c05f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=752115470 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_csr_rw.752115470
Directory /workspace/3.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_intr_test.2062166605
Short name T173
Test name
Test status
Simulation time 36404259 ps
CPU time 0.68 seconds
Started Aug 14 04:31:29 PM PDT 24
Finished Aug 14 04:31:30 PM PDT 24
Peak memory 206864 kb
Host smart-1e4d7a0d-bffe-43bd-a80c-f707e85cbb46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2062166605 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_intr_test.2062166605
Directory /workspace/3.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_partial_access.450141693
Short name T139
Test name
Test status
Simulation time 158480971 ps
CPU time 2.19 seconds
Started Aug 14 04:30:57 PM PDT 24
Finished Aug 14 04:31:00 PM PDT 24
Peak memory 207060 kb
Host smart-f2735864-1865-4679-8aaa-5e2d05edd6bf
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=450141693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_partial_access.450141693
Directory /workspace/3.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_mem_walk.2447529157
Short name T94
Test name
Test status
Simulation time 161591052 ps
CPU time 3.83 seconds
Started Aug 14 04:31:17 PM PDT 24
Finished Aug 14 04:31:21 PM PDT 24
Peak memory 206964 kb
Host smart-6d090fee-89b6-4ff7-9585-6770fa2aebaf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2447529157 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_mem_walk.2447529157
Directory /workspace/3.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_same_csr_outstanding.1329137697
Short name T52
Test name
Test status
Simulation time 228942187 ps
CPU time 1.59 seconds
Started Aug 14 04:31:10 PM PDT 24
Finished Aug 14 04:31:12 PM PDT 24
Peak memory 207172 kb
Host smart-8c874193-b774-417c-9d14-b23958df62bf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1329137697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_same_csr_outstanding.1329137697
Directory /workspace/3.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_errors.3952188026
Short name T50
Test name
Test status
Simulation time 261149082 ps
CPU time 3.61 seconds
Started Aug 14 04:31:12 PM PDT 24
Finished Aug 14 04:31:16 PM PDT 24
Peak memory 215384 kb
Host smart-580baf7c-646a-43ea-9ec7-1b0c7e077f49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3952188026 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_errors.3952188026
Directory /workspace/3.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.usbdev_tl_intg_err.1177271845
Short name T67
Test name
Test status
Simulation time 734916435 ps
CPU time 4.61 seconds
Started Aug 14 04:31:00 PM PDT 24
Finished Aug 14 04:31:05 PM PDT 24
Peak memory 207144 kb
Host smart-927488b3-2324-466e-986d-5dc610d90ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1177271845 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.usbdev_tl_intg_err.1177271845
Directory /workspace/3.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.usbdev_intr_test.3005375648
Short name T77
Test name
Test status
Simulation time 44494014 ps
CPU time 0.72 seconds
Started Aug 14 04:31:14 PM PDT 24
Finished Aug 14 04:31:15 PM PDT 24
Peak memory 206808 kb
Host smart-3cf13081-d388-4dab-ad74-5136febd643e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3005375648 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.usbdev_intr_test.3005375648
Directory /workspace/30.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.usbdev_intr_test.2118067419
Short name T61
Test name
Test status
Simulation time 31369370 ps
CPU time 0.68 seconds
Started Aug 14 04:31:19 PM PDT 24
Finished Aug 14 04:31:20 PM PDT 24
Peak memory 206820 kb
Host smart-e2afe5f1-b8fc-40c0-8375-9ce57035f1c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2118067419 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.usbdev_intr_test.2118067419
Directory /workspace/31.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.usbdev_intr_test.8717864
Short name T143
Test name
Test status
Simulation time 38734719 ps
CPU time 0.72 seconds
Started Aug 14 04:31:25 PM PDT 24
Finished Aug 14 04:31:25 PM PDT 24
Peak memory 206760 kb
Host smart-2cc4d32a-14f4-4fa5-bfdb-323f18cdae82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=8717864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.usbdev_intr_test.8717864
Directory /workspace/33.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.usbdev_intr_test.2927927293
Short name T156
Test name
Test status
Simulation time 41595893 ps
CPU time 0.68 seconds
Started Aug 14 04:31:40 PM PDT 24
Finished Aug 14 04:31:41 PM PDT 24
Peak memory 206872 kb
Host smart-9a39ec3d-0973-42e4-8fe6-95c9cafce0dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2927927293 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.usbdev_intr_test.2927927293
Directory /workspace/34.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.usbdev_intr_test.25172970
Short name T114
Test name
Test status
Simulation time 46180700 ps
CPU time 0.7 seconds
Started Aug 14 04:31:33 PM PDT 24
Finished Aug 14 04:31:34 PM PDT 24
Peak memory 206832 kb
Host smart-4e11f078-6878-40c6-a87a-540cd3d940cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=25172970 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.usbdev_intr_test.25172970
Directory /workspace/35.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.usbdev_intr_test.2245332529
Short name T105
Test name
Test status
Simulation time 37089502 ps
CPU time 0.68 seconds
Started Aug 14 04:31:30 PM PDT 24
Finished Aug 14 04:31:31 PM PDT 24
Peak memory 206812 kb
Host smart-cf66389d-cb74-4724-9185-2ea9f86fc1cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2245332529 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.usbdev_intr_test.2245332529
Directory /workspace/36.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.usbdev_intr_test.3647237122
Short name T56
Test name
Test status
Simulation time 52978820 ps
CPU time 0.73 seconds
Started Aug 14 04:31:30 PM PDT 24
Finished Aug 14 04:31:31 PM PDT 24
Peak memory 206840 kb
Host smart-56cc265d-4db0-4e02-8b3a-fb0935b277f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3647237122 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.usbdev_intr_test.3647237122
Directory /workspace/37.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.usbdev_intr_test.754769174
Short name T99
Test name
Test status
Simulation time 46370138 ps
CPU time 0.71 seconds
Started Aug 14 04:31:33 PM PDT 24
Finished Aug 14 04:31:34 PM PDT 24
Peak memory 206824 kb
Host smart-80b11a91-71c3-46df-af06-5bf04aa0d435
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=754769174 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.usbdev_intr_test.754769174
Directory /workspace/38.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.usbdev_intr_test.1885693697
Short name T120
Test name
Test status
Simulation time 43738852 ps
CPU time 0.72 seconds
Started Aug 14 04:31:24 PM PDT 24
Finished Aug 14 04:31:24 PM PDT 24
Peak memory 206836 kb
Host smart-959ca6b5-8163-463d-80b8-4291c8652ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1885693697 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.usbdev_intr_test.1885693697
Directory /workspace/39.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_aliasing.156569462
Short name T41
Test name
Test status
Simulation time 357006969 ps
CPU time 3.51 seconds
Started Aug 14 04:31:12 PM PDT 24
Finished Aug 14 04:31:21 PM PDT 24
Peak memory 207096 kb
Host smart-7a25713c-8a31-46cd-944d-1db6c33fcf71
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=156569462 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_aliasing.156569462
Directory /workspace/4.usbdev_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_bit_bash.1371837633
Short name T40
Test name
Test status
Simulation time 830208298 ps
CPU time 4.61 seconds
Started Aug 14 04:31:02 PM PDT 24
Finished Aug 14 04:31:07 PM PDT 24
Peak memory 207140 kb
Host smart-88c5f458-f9f3-4a0d-b1ab-2e5058844a55
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1371837633 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_bit_bash.1371837633
Directory /workspace/4.usbdev_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_mem_rw_with_rand_reset.246655887
Short name T133
Test name
Test status
Simulation time 71219672 ps
CPU time 1.52 seconds
Started Aug 14 04:31:17 PM PDT 24
Finished Aug 14 04:31:19 PM PDT 24
Peak memory 215452 kb
Host smart-4a283494-f760-4552-8405-b6f77e2f4c6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246655887 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev
_csr_mem_rw_with_rand_reset.246655887
Directory /workspace/4.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_csr_rw.1588367608
Short name T138
Test name
Test status
Simulation time 87391100 ps
CPU time 1.06 seconds
Started Aug 14 04:31:12 PM PDT 24
Finished Aug 14 04:31:13 PM PDT 24
Peak memory 206896 kb
Host smart-d63ed335-3acf-432a-83ac-6016709ccbad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1588367608 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_csr_rw.1588367608
Directory /workspace/4.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_intr_test.3006795461
Short name T152
Test name
Test status
Simulation time 41994545 ps
CPU time 0.68 seconds
Started Aug 14 04:31:26 PM PDT 24
Finished Aug 14 04:31:26 PM PDT 24
Peak memory 206824 kb
Host smart-167fb02c-5aab-4e54-9a23-633448c509c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3006795461 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_intr_test.3006795461
Directory /workspace/4.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_partial_access.4223941855
Short name T167
Test name
Test status
Simulation time 118504535 ps
CPU time 1.55 seconds
Started Aug 14 04:31:12 PM PDT 24
Finished Aug 14 04:31:14 PM PDT 24
Peak memory 215532 kb
Host smart-1ca4bd73-0171-4137-8ce9-d94aafd90a66
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw
/dv/tools/sim.tcl +ntb_random_seed=4223941855 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_partial_access.4223941855
Directory /workspace/4.usbdev_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_mem_walk.1971218657
Short name T128
Test name
Test status
Simulation time 721309409 ps
CPU time 4.68 seconds
Started Aug 14 04:31:07 PM PDT 24
Finished Aug 14 04:31:12 PM PDT 24
Peak memory 207000 kb
Host smart-f4ed72c5-9890-408d-b77c-c56bb964ee21
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1971218657 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_mem_walk.1971218657
Directory /workspace/4.usbdev_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_same_csr_outstanding.29248184
Short name T87
Test name
Test status
Simulation time 96354596 ps
CPU time 1.52 seconds
Started Aug 14 04:31:13 PM PDT 24
Finished Aug 14 04:31:15 PM PDT 24
Peak memory 207152 kb
Host smart-d0e6bbae-6557-489f-8507-8705703e63a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=29248184 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_same_csr_outstanding.29248184
Directory /workspace/4.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_errors.702429222
Short name T161
Test name
Test status
Simulation time 69019246 ps
CPU time 1.35 seconds
Started Aug 14 04:31:19 PM PDT 24
Finished Aug 14 04:31:21 PM PDT 24
Peak memory 207108 kb
Host smart-190e9313-5e32-4613-8ddd-c1caa2686300
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=702429222 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_errors.702429222
Directory /workspace/4.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.usbdev_tl_intg_err.3778489803
Short name T66
Test name
Test status
Simulation time 576666407 ps
CPU time 2.73 seconds
Started Aug 14 04:31:03 PM PDT 24
Finished Aug 14 04:31:05 PM PDT 24
Peak memory 207156 kb
Host smart-67053569-2deb-4af6-aa95-426a819dee4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3778489803 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.usbdev_tl_intg_err.3778489803
Directory /workspace/4.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.usbdev_intr_test.2094190990
Short name T162
Test name
Test status
Simulation time 61082784 ps
CPU time 0.78 seconds
Started Aug 14 04:31:26 PM PDT 24
Finished Aug 14 04:31:27 PM PDT 24
Peak memory 206732 kb
Host smart-82e7f7f1-c918-4762-a180-ece6e1988758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2094190990 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.usbdev_intr_test.2094190990
Directory /workspace/40.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.usbdev_intr_test.1438311693
Short name T62
Test name
Test status
Simulation time 61343729 ps
CPU time 0.73 seconds
Started Aug 14 04:31:40 PM PDT 24
Finished Aug 14 04:31:41 PM PDT 24
Peak memory 206828 kb
Host smart-beb58684-9371-45da-9951-9eccc87a977d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1438311693 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.usbdev_intr_test.1438311693
Directory /workspace/41.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.usbdev_intr_test.3585255110
Short name T9
Test name
Test status
Simulation time 71828318 ps
CPU time 0.73 seconds
Started Aug 14 04:31:51 PM PDT 24
Finished Aug 14 04:31:52 PM PDT 24
Peak memory 206792 kb
Host smart-27050ff1-84d1-45af-8658-23423d01dca2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3585255110 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.usbdev_intr_test.3585255110
Directory /workspace/43.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.usbdev_intr_test.2833272501
Short name T64
Test name
Test status
Simulation time 58851695 ps
CPU time 0.74 seconds
Started Aug 14 04:31:47 PM PDT 24
Finished Aug 14 04:31:48 PM PDT 24
Peak memory 206868 kb
Host smart-84b9ef41-6dfe-41b7-b714-26ca1c47498a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2833272501 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.usbdev_intr_test.2833272501
Directory /workspace/44.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.usbdev_intr_test.2559629416
Short name T90
Test name
Test status
Simulation time 61874886 ps
CPU time 0.74 seconds
Started Aug 14 04:31:24 PM PDT 24
Finished Aug 14 04:31:25 PM PDT 24
Peak memory 206808 kb
Host smart-8009260b-4760-43ee-bbd4-24ed40dc9c1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2559629416 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.usbdev_intr_test.2559629416
Directory /workspace/45.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.usbdev_intr_test.1324252551
Short name T132
Test name
Test status
Simulation time 78817280 ps
CPU time 0.75 seconds
Started Aug 14 04:31:24 PM PDT 24
Finished Aug 14 04:31:25 PM PDT 24
Peak memory 206780 kb
Host smart-5b85b9e5-a169-4ffc-a057-83e9f3f4a35c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1324252551 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.usbdev_intr_test.1324252551
Directory /workspace/46.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.usbdev_intr_test.859286516
Short name T116
Test name
Test status
Simulation time 47888857 ps
CPU time 0.76 seconds
Started Aug 14 04:31:44 PM PDT 24
Finished Aug 14 04:31:45 PM PDT 24
Peak memory 206808 kb
Host smart-ac77e06f-c19f-4499-955c-b9c526dbc07c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=859286516 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.usbdev_intr_test.859286516
Directory /workspace/47.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.usbdev_intr_test.2251138568
Short name T20
Test name
Test status
Simulation time 77622641 ps
CPU time 0.75 seconds
Started Aug 14 04:31:24 PM PDT 24
Finished Aug 14 04:31:25 PM PDT 24
Peak memory 206820 kb
Host smart-939daed2-5303-4fbc-98a0-094898f6e56e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2251138568 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.usbdev_intr_test.2251138568
Directory /workspace/48.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.usbdev_intr_test.1664700324
Short name T174
Test name
Test status
Simulation time 42311136 ps
CPU time 0.71 seconds
Started Aug 14 04:31:22 PM PDT 24
Finished Aug 14 04:31:23 PM PDT 24
Peak memory 206832 kb
Host smart-7e4cb26e-7d86-4b7f-8d53-666e4ab15cd3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1664700324 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.usbdev_intr_test.1664700324
Directory /workspace/49.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_mem_rw_with_rand_reset.2822045864
Short name T53
Test name
Test status
Simulation time 182254223 ps
CPU time 1.89 seconds
Started Aug 14 04:31:34 PM PDT 24
Finished Aug 14 04:31:36 PM PDT 24
Peak memory 215404 kb
Host smart-78a13dec-5e37-4660-8e84-49574fa55396
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822045864 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbde
v_csr_mem_rw_with_rand_reset.2822045864
Directory /workspace/5.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_csr_rw.363339130
Short name T44
Test name
Test status
Simulation time 53626113 ps
CPU time 0.82 seconds
Started Aug 14 04:31:31 PM PDT 24
Finished Aug 14 04:31:32 PM PDT 24
Peak memory 206900 kb
Host smart-02e866dd-076e-46bb-bb2e-cc18dd215b5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=363339130 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_csr_rw.363339130
Directory /workspace/5.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_intr_test.976496655
Short name T153
Test name
Test status
Simulation time 53222460 ps
CPU time 0.73 seconds
Started Aug 14 04:31:11 PM PDT 24
Finished Aug 14 04:31:12 PM PDT 24
Peak memory 206820 kb
Host smart-8cffd9a4-f239-4bad-a1bb-27d9d63c7989
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=976496655 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_intr_test.976496655
Directory /workspace/5.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_same_csr_outstanding.155139318
Short name T10
Test name
Test status
Simulation time 135013375 ps
CPU time 1.21 seconds
Started Aug 14 04:31:16 PM PDT 24
Finished Aug 14 04:31:17 PM PDT 24
Peak memory 206992 kb
Host smart-cfb16cd8-a7d8-4f7c-bb4b-c41d70e409a8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=155139318 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_same_csr_outstanding.155139318
Directory /workspace/5.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_errors.2158318472
Short name T109
Test name
Test status
Simulation time 86545946 ps
CPU time 1.62 seconds
Started Aug 14 04:31:05 PM PDT 24
Finished Aug 14 04:31:07 PM PDT 24
Peak memory 215360 kb
Host smart-a5c5a106-3296-470d-bde2-f769277a3beb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2158318472 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_errors.2158318472
Directory /workspace/5.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.usbdev_tl_intg_err.3385781431
Short name T102
Test name
Test status
Simulation time 451006595 ps
CPU time 2.82 seconds
Started Aug 14 04:31:08 PM PDT 24
Finished Aug 14 04:31:11 PM PDT 24
Peak memory 207156 kb
Host smart-8479050a-77a0-4ad3-83ba-37cddef2d832
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3385781431 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.usbdev_tl_intg_err.3385781431
Directory /workspace/5.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_mem_rw_with_rand_reset.3783281334
Short name T108
Test name
Test status
Simulation time 167838648 ps
CPU time 1.75 seconds
Started Aug 14 04:31:13 PM PDT 24
Finished Aug 14 04:31:15 PM PDT 24
Peak memory 215340 kb
Host smart-d3c761e5-2c07-48ee-9e11-68fcd01d4b20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783281334 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbde
v_csr_mem_rw_with_rand_reset.3783281334
Directory /workspace/6.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_csr_rw.3665588728
Short name T159
Test name
Test status
Simulation time 69065680 ps
CPU time 0.88 seconds
Started Aug 14 04:31:19 PM PDT 24
Finished Aug 14 04:31:20 PM PDT 24
Peak memory 206896 kb
Host smart-84b58335-23f7-48b1-873d-6a5162d0be7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3665588728 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_csr_rw.3665588728
Directory /workspace/6.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_intr_test.3594134232
Short name T101
Test name
Test status
Simulation time 48927920 ps
CPU time 0.71 seconds
Started Aug 14 04:31:18 PM PDT 24
Finished Aug 14 04:31:19 PM PDT 24
Peak memory 206808 kb
Host smart-ab372b39-c461-40ab-a898-91507b984278
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3594134232 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_intr_test.3594134232
Directory /workspace/6.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_same_csr_outstanding.3199740823
Short name T135
Test name
Test status
Simulation time 104238196 ps
CPU time 1.06 seconds
Started Aug 14 04:31:16 PM PDT 24
Finished Aug 14 04:31:17 PM PDT 24
Peak memory 207152 kb
Host smart-6101be62-dc1d-4301-9c90-1df00c3dfe0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3199740823 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_same_csr_outstanding.3199740823
Directory /workspace/6.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_errors.2568176405
Short name T49
Test name
Test status
Simulation time 238725023 ps
CPU time 2.87 seconds
Started Aug 14 04:31:18 PM PDT 24
Finished Aug 14 04:31:21 PM PDT 24
Peak memory 219812 kb
Host smart-9ff20319-7ff9-4405-896e-f94b507f1d95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2568176405 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_errors.2568176405
Directory /workspace/6.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.usbdev_tl_intg_err.1488567288
Short name T160
Test name
Test status
Simulation time 445583363 ps
CPU time 2.84 seconds
Started Aug 14 04:31:14 PM PDT 24
Finished Aug 14 04:31:17 PM PDT 24
Peak memory 207216 kb
Host smart-76756ff9-4e20-47e0-8fe9-555741d17ec2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1488567288 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.usbdev_tl_intg_err.1488567288
Directory /workspace/6.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_mem_rw_with_rand_reset.1997688265
Short name T4
Test name
Test status
Simulation time 181542721 ps
CPU time 1.92 seconds
Started Aug 14 04:31:33 PM PDT 24
Finished Aug 14 04:31:35 PM PDT 24
Peak memory 215484 kb
Host smart-aeb13d4c-01d3-44ad-b214-15d46ce0531c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997688265 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbde
v_csr_mem_rw_with_rand_reset.1997688265
Directory /workspace/7.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_csr_rw.4062095678
Short name T75
Test name
Test status
Simulation time 70943909 ps
CPU time 0.88 seconds
Started Aug 14 04:31:30 PM PDT 24
Finished Aug 14 04:31:32 PM PDT 24
Peak memory 206932 kb
Host smart-bdd7d6dd-34aa-4377-b51b-5db0132fe3e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4062095678 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_csr_rw.4062095678
Directory /workspace/7.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_intr_test.3845922670
Short name T144
Test name
Test status
Simulation time 63239836 ps
CPU time 0.72 seconds
Started Aug 14 04:31:19 PM PDT 24
Finished Aug 14 04:31:20 PM PDT 24
Peak memory 206824 kb
Host smart-c22e9a96-fa53-4040-b807-fc3855edd5ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3845922670 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_intr_test.3845922670
Directory /workspace/7.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_same_csr_outstanding.4112775162
Short name T150
Test name
Test status
Simulation time 226553551 ps
CPU time 1.17 seconds
Started Aug 14 04:31:31 PM PDT 24
Finished Aug 14 04:31:35 PM PDT 24
Peak memory 207208 kb
Host smart-24f5e274-a5b0-414a-ab68-80c4ea30a3f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4112775162 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_same_csr_outstanding.4112775162
Directory /workspace/7.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_errors.4213604097
Short name T122
Test name
Test status
Simulation time 243729366 ps
CPU time 2.5 seconds
Started Aug 14 04:31:19 PM PDT 24
Finished Aug 14 04:31:22 PM PDT 24
Peak memory 220896 kb
Host smart-ae3e8c94-7942-45e5-b2e9-1653ca5a1a33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4213604097 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_errors.4213604097
Directory /workspace/7.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.usbdev_tl_intg_err.1465822676
Short name T71
Test name
Test status
Simulation time 744259861 ps
CPU time 4.63 seconds
Started Aug 14 04:31:23 PM PDT 24
Finished Aug 14 04:31:28 PM PDT 24
Peak memory 207152 kb
Host smart-89239ec9-3b67-43cd-b4db-6ea0ec9f5a8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1465822676 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.usbdev_tl_intg_err.1465822676
Directory /workspace/7.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_mem_rw_with_rand_reset.2640649972
Short name T85
Test name
Test status
Simulation time 64370860 ps
CPU time 1.15 seconds
Started Aug 14 04:31:26 PM PDT 24
Finished Aug 14 04:31:28 PM PDT 24
Peak memory 215480 kb
Host smart-dcd351cf-7a11-42e2-8b07-32736af5c9fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640649972 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ
=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbde
v_csr_mem_rw_with_rand_reset.2640649972
Directory /workspace/8.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_csr_rw.1681923848
Short name T43
Test name
Test status
Simulation time 93092135 ps
CPU time 1.06 seconds
Started Aug 14 04:31:18 PM PDT 24
Finished Aug 14 04:31:19 PM PDT 24
Peak memory 206912 kb
Host smart-7e121653-b822-4cda-af1a-98bedbcd8550
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1681923848 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_csr_rw.1681923848
Directory /workspace/8.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_intr_test.183978751
Short name T63
Test name
Test status
Simulation time 65803676 ps
CPU time 0.71 seconds
Started Aug 14 04:31:23 PM PDT 24
Finished Aug 14 04:31:24 PM PDT 24
Peak memory 206812 kb
Host smart-6b5a2b59-9364-42f1-bdcd-8d50257e70f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=183978751 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_intr_test.183978751
Directory /workspace/8.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_same_csr_outstanding.3125810838
Short name T175
Test name
Test status
Simulation time 144045281 ps
CPU time 1.43 seconds
Started Aug 14 04:31:20 PM PDT 24
Finished Aug 14 04:31:21 PM PDT 24
Peak memory 207188 kb
Host smart-0c98fd18-c4d6-4897-989a-299d3330773d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3125810838 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_same_csr_outstanding.3125810838
Directory /workspace/8.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_errors.946799436
Short name T140
Test name
Test status
Simulation time 117825682 ps
CPU time 1.48 seconds
Started Aug 14 04:31:27 PM PDT 24
Finished Aug 14 04:31:28 PM PDT 24
Peak memory 207160 kb
Host smart-350caeef-bf11-4f10-9805-6e38fc0c9335
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=946799436 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_errors.946799436
Directory /workspace/8.usbdev_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.usbdev_tl_intg_err.1139267642
Short name T70
Test name
Test status
Simulation time 654019250 ps
CPU time 4.42 seconds
Started Aug 14 04:31:21 PM PDT 24
Finished Aug 14 04:31:26 PM PDT 24
Peak memory 207228 kb
Host smart-513ce98b-4935-49d4-b3c9-6a7cc6c8d448
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1139267642 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.usbdev_tl_intg_err.1139267642
Directory /workspace/8.usbdev_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_mem_rw_with_rand_reset.442921198
Short name T84
Test name
Test status
Simulation time 138651300 ps
CPU time 1.88 seconds
Started Aug 14 04:31:44 PM PDT 24
Finished Aug 14 04:31:46 PM PDT 24
Peak memory 215404 kb
Host smart-7f648e56-973e-4bc2-bf41-ae0c00f761f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442921198 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=
usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev
_csr_mem_rw_with_rand_reset.442921198
Directory /workspace/9.usbdev_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_csr_rw.1169574312
Short name T171
Test name
Test status
Simulation time 59113338 ps
CPU time 0.81 seconds
Started Aug 14 04:31:13 PM PDT 24
Finished Aug 14 04:31:14 PM PDT 24
Peak memory 206892 kb
Host smart-43bda553-3e76-4904-b63d-bc1447c542e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1169574312 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_csr_rw.1169574312
Directory /workspace/9.usbdev_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_intr_test.4245998571
Short name T88
Test name
Test status
Simulation time 42320291 ps
CPU time 0.71 seconds
Started Aug 14 04:31:17 PM PDT 24
Finished Aug 14 04:31:18 PM PDT 24
Peak memory 206836 kb
Host smart-04f7f84c-6195-4ce6-b7ed-2c134bd86bf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4245998571 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_intr_test.4245998571
Directory /workspace/9.usbdev_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_same_csr_outstanding.3721278088
Short name T34
Test name
Test status
Simulation time 173074343 ps
CPU time 1.26 seconds
Started Aug 14 04:31:15 PM PDT 24
Finished Aug 14 04:31:16 PM PDT 24
Peak memory 207196 kb
Host smart-283f3bca-752c-4c81-afe8-6ba56bfc0519
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3721278088 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_same_csr_outstanding.3721278088
Directory /workspace/9.usbdev_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.usbdev_tl_intg_err.4192787837
Short name T115
Test name
Test status
Simulation time 339511894 ps
CPU time 2.24 seconds
Started Aug 14 04:31:21 PM PDT 24
Finished Aug 14 04:31:23 PM PDT 24
Peak memory 207200 kb
Host smart-73a8b4c6-e5a2-479b-aab0-468281acf647
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4192787837 -assert nopostproc +UVM_TESTNAME=usbdev_base_test +UVM_TEST_SEQ=usbdev_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.usbdev_tl_intg_err.4192787837
Directory /workspace/9.usbdev_tl_intg_err/latest
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