Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.94	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	22	0	22	100.00
Crosses	72	1	71	98.61

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	18	0	18	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	72	1	71	98.61	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	368	1			T1	8		T9	5		T6	2
all_pins[1]	368	1			T1	8		T9	5		T6	2
all_pins[2]	368	1			T1	8		T9	5		T6	2
all_pins[3]	368	1			T1	8		T9	5		T6	2
all_pins[4]	368	1			T1	8		T9	5		T6	2
all_pins[5]	368	1			T1	8		T9	5		T6	2
all_pins[6]	368	1			T1	8		T9	5		T6	2
all_pins[7]	368	1			T1	8		T9	5		T6	2
all_pins[8]	368	1			T1	8		T9	5		T6	2
all_pins[9]	368	1			T1	8		T9	5		T6	2
all_pins[10]	368	1			T1	8		T9	5		T6	2
all_pins[11]	368	1			T1	8		T9	5		T6	2
all_pins[12]	368	1			T1	8		T9	5		T6	2
all_pins[13]	368	1			T1	8		T9	5		T6	2
all_pins[14]	368	1			T1	8		T9	5		T6	2
all_pins[15]	368	1			T1	8		T9	5		T6	2
all_pins[16]	368	1			T1	8		T9	5		T6	2
all_pins[17]	368	1			T1	8		T9	5		T6	2

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	10643	1			T1	235		T9	136		T6	64
values[0x1]	1133	1			T1	21		T9	24		T18	22
transitions[0x0=>0x1]	858	1			T1	15		T9	15		T18	12
transitions[0x1=>0x0]	858	1			T1	15		T9	15		T18	12

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	72	1	71	98.61	1

Automatically Generated Cross Bins for cp_intr_pins_all_values

Uncovered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	NUMBER	STATUS
[all_pins[17]]	[transitions[0x1=>0x0]]	0	1	1

Covered bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	301	1			T1	6		T9	2		T6	2
all_pins[0]	values[0x1]	67	1			T1	2		T9	3		T18	1
all_pins[0]	transitions[0x0=>0x1]	52	1			T1	2		T9	2		T18	1
all_pins[0]	transitions[0x1=>0x0]	36	1			T1	1		T18	2		T19	3
all_pins[1]	values[0x0]	317	1			T1	7		T9	4		T6	2
all_pins[1]	values[0x1]	51	1			T1	1		T9	1		T18	2
all_pins[1]	transitions[0x0=>0x1]	36	1			T1	1		T9	1		T19	2
all_pins[1]	transitions[0x1=>0x0]	65	1			T1	1		T9	1		T18	2
all_pins[2]	values[0x0]	288	1			T1	7		T9	4		T6	2
all_pins[2]	values[0x1]	80	1			T1	1		T9	1		T18	4
all_pins[2]	transitions[0x0=>0x1]	53	1			T18	2		T19	2		T20	1
all_pins[2]	transitions[0x1=>0x0]	53	1			T1	1		T9	2		T19	3
all_pins[3]	values[0x0]	288	1			T1	6		T9	2		T6	2
all_pins[3]	values[0x1]	80	1			T1	2		T9	3		T18	2
all_pins[3]	transitions[0x0=>0x1]	61	1			T1	1		T9	1		T19	3
all_pins[3]	transitions[0x1=>0x0]	43	1			T20	2		T21	3		T57	1
all_pins[4]	values[0x0]	306	1			T1	7		T9	3		T6	2
all_pins[4]	values[0x1]	62	1			T1	1		T9	2		T18	2
all_pins[4]	transitions[0x0=>0x1]	46	1			T18	2		T20	2		T21	3
all_pins[4]	transitions[0x1=>0x0]	43	1			T1	1		T20	1		T21	1
all_pins[5]	values[0x0]	309	1			T1	6		T9	3		T6	2
all_pins[5]	values[0x1]	59	1			T1	2		T9	2		T20	1
all_pins[5]	transitions[0x0=>0x1]	47	1			T1	2		T9	2		T20	1
all_pins[5]	transitions[0x1=>0x0]	50	1			T9	1		T20	1		T21	1
all_pins[6]	values[0x0]	306	1			T1	8		T9	4		T6	2
all_pins[6]	values[0x1]	62	1			T9	1		T20	1		T21	1
all_pins[6]	transitions[0x0=>0x1]	47	1			T9	1		T20	1		T21	1
all_pins[6]	transitions[0x1=>0x0]	46	1			T1	2		T18	1		T20	1
all_pins[7]	values[0x0]	307	1			T1	6		T9	5		T6	2
all_pins[7]	values[0x1]	61	1			T1	2		T18	1		T20	1
all_pins[7]	transitions[0x0=>0x1]	44	1			T1	2		T18	1		T20	1
all_pins[7]	transitions[0x1=>0x0]	32	1			T18	1		T19	1		T20	2
all_pins[8]	values[0x0]	319	1			T1	8		T9	5		T6	2
all_pins[8]	values[0x1]	49	1			T18	1		T19	1		T20	2
all_pins[8]	transitions[0x0=>0x1]	42	1			T19	1		T20	2		T62	2
all_pins[8]	transitions[0x1=>0x0]	45	1			T9	1		T18	1		T19	4
all_pins[9]	values[0x0]	316	1			T1	8		T9	4		T6	2
all_pins[9]	values[0x1]	52	1			T9	1		T18	2		T19	4
all_pins[9]	transitions[0x0=>0x1]	40	1			T9	1		T18	1		T19	2
all_pins[9]	transitions[0x1=>0x0]	60	1			T1	3		T9	2		T19	1
all_pins[10]	values[0x0]	296	1			T1	5		T9	3		T6	2
all_pins[10]	values[0x1]	72	1			T1	3		T9	2		T18	1
all_pins[10]	transitions[0x0=>0x1]	60	1			T1	3		T9	2		T18	1
all_pins[10]	transitions[0x1=>0x0]	46	1			T19	1		T20	2		T21	1
all_pins[11]	values[0x0]	310	1			T1	8		T9	5		T6	2
all_pins[11]	values[0x1]	58	1			T19	1		T20	2		T21	1
all_pins[11]	transitions[0x0=>0x1]	38	1			T20	2		T21	1		T62	1
all_pins[11]	transitions[0x1=>0x0]	52	1			T9	1		T18	2		T19	3
all_pins[12]	values[0x0]	296	1			T1	8		T9	4		T6	2
all_pins[12]	values[0x1]	72	1			T9	1		T18	2		T19	4
all_pins[12]	transitions[0x0=>0x1]	46	1			T18	1		T19	4		T20	1
all_pins[12]	transitions[0x1=>0x0]	43	1			T1	1		T20	1		T21	2
all_pins[13]	values[0x0]	299	1			T1	7		T9	4		T6	2
all_pins[13]	values[0x1]	69	1			T1	1		T9	1		T18	1
all_pins[13]	transitions[0x0=>0x1]	53	1			T9	1		T18	1		T20	1
all_pins[13]	transitions[0x1=>0x0]	33	1			T20	1		T21	1		T57	2
all_pins[14]	values[0x0]	319	1			T1	7		T9	5		T6	2
all_pins[14]	values[0x1]	49	1			T1	1		T20	1		T21	2
all_pins[14]	transitions[0x0=>0x1]	37	1			T20	1		T21	2		T56	1
all_pins[14]	transitions[0x1=>0x0]	64	1			T9	3		T18	2		T19	2
all_pins[15]	values[0x0]	292	1			T1	7		T9	2		T6	2
all_pins[15]	values[0x1]	76	1			T1	1		T9	3		T18	2
all_pins[15]	transitions[0x0=>0x1]	56	1			T9	1		T18	1		T21	3
all_pins[15]	transitions[0x1=>0x0]	41	1			T1	1		T9	1		T21	1
all_pins[16]	values[0x0]	307	1			T1	6		T9	2		T6	2
all_pins[16]	values[0x1]	61	1			T1	2		T9	3		T18	1
all_pins[16]	transitions[0x0=>0x1]	47	1			T1	2		T9	3		T18	1
all_pins[16]	transitions[0x1=>0x0]	39	1			T1	2		T19	2		T21	1
all_pins[17]	values[0x0]	315	1			T1	6		T9	5		T6	2
all_pins[17]	values[0x1]	53	1			T1	2		T19	3		T21	1
all_pins[17]	transitions[0x0=>0x1]	53	1			T1	2		T19	3		T21	1