Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.42	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	24	0	24	100.00
Crosses	108	10	98	90.74

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	18	0	18	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=17}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	108	10	98	90.74	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	18	0	18	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	278	1			T1	7		T9	4		T18	4
all_values[1]	278	1			T1	7		T9	4		T18	4
all_values[2]	278	1			T1	7		T9	4		T18	4
all_values[3]	278	1			T1	7		T9	4		T18	4
all_values[4]	278	1			T1	7		T9	4		T18	4
all_values[5]	278	1			T1	7		T9	4		T18	4
all_values[6]	278	1			T1	7		T9	4		T18	4
all_values[7]	278	1			T1	7		T9	4		T18	4
all_values[8]	278	1			T1	7		T9	4		T18	4
all_values[9]	278	1			T1	7		T9	4		T18	4
all_values[10]	278	1			T1	7		T9	4		T18	4
all_values[11]	278	1			T1	7		T9	4		T18	4
all_values[12]	278	1			T1	7		T9	4		T18	4
all_values[13]	278	1			T1	7		T9	4		T18	4
all_values[14]	278	1			T1	7		T9	4		T18	4
all_values[15]	278	1			T1	7		T9	4		T18	4
all_values[16]	278	1			T1	7		T9	4		T18	4
all_values[17]	278	1			T1	7		T9	4		T18	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6646

1

T1

168

T9

93

T18

98

auto[1]

2250

1

T1

56

T9

35

T18

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6132

1

T1

162

T9

86

T18

84

auto[1]

2764

1

T1

62

T9

42

T18

44

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5262

1

T1

121

T9

82

T18

80

auto[1]

3634

1

T1

103

T9

46

T18

48

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	108	10	98	90.74	10
Automatically Generated Cross Bins	108	10	98	90.74	10
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[0] , all_values[1]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[7] , all_values[8]]	[auto[0]]	*	[auto[1]]	--	--	4
[all_values[17]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	80	1			T1	2		T18	2		T19	3
all_values[0]	auto[0]	auto[1]	auto[0]	72	1			T1	1		T9	1		T19	2
all_values[0]	auto[1]	auto[0]	auto[1]	69	1			T1	3		T18	1		T19	1
all_values[0]	auto[1]	auto[1]	auto[1]	57	1			T1	1		T9	3		T18	1
all_values[1]	auto[0]	auto[0]	auto[0]	95	1			T1	4		T18	1		T19	1
all_values[1]	auto[0]	auto[1]	auto[0]	71	1			T1	1		T9	1		T18	1
all_values[1]	auto[1]	auto[0]	auto[1]	70	1			T1	1		T9	3		T19	2
all_values[1]	auto[1]	auto[1]	auto[1]	42	1			T1	1		T18	2		T19	2
all_values[2]	auto[0]	auto[0]	auto[0]	55	1			T1	2		T19	2		T21	2
all_values[2]	auto[0]	auto[0]	auto[1]	30	1			T9	1		T20	1		T56	1
all_values[2]	auto[0]	auto[1]	auto[0]	51	1			T1	2		T9	1		T19	2
all_values[2]	auto[0]	auto[1]	auto[1]	39	1			T1	1		T18	3		T20	1
all_values[2]	auto[1]	auto[0]	auto[1]	51	1			T1	1		T20	3		T21	1
all_values[2]	auto[1]	auto[1]	auto[1]	52	1			T1	1		T9	2		T18	1
all_values[3]	auto[0]	auto[0]	auto[0]	47	1			T1	1		T9	1		T18	1
all_values[3]	auto[0]	auto[0]	auto[1]	28	1			T19	1		T20	2		T21	1
all_values[3]	auto[0]	auto[1]	auto[0]	47	1			T1	1		T19	1		T20	2
all_values[3]	auto[0]	auto[1]	auto[1]	30	1			T9	1		T18	2		T19	2
all_values[3]	auto[1]	auto[0]	auto[1]	61	1			T1	1		T9	1		T18	1
all_values[3]	auto[1]	auto[1]	auto[1]	65	1			T1	4		T9	1		T19	1
all_values[4]	auto[0]	auto[0]	auto[0]	63	1			T1	2		T19	4		T21	1
all_values[4]	auto[0]	auto[0]	auto[1]	23	1			T20	2		T21	1		T61	1
all_values[4]	auto[0]	auto[1]	auto[0]	54	1			T1	1		T9	2		T18	2
all_values[4]	auto[0]	auto[1]	auto[1]	27	1			T1	1		T9	1		T18	1
all_values[4]	auto[1]	auto[0]	auto[1]	62	1			T1	2		T9	1		T19	3
all_values[4]	auto[1]	auto[1]	auto[1]	49	1			T1	1		T18	1		T20	2
all_values[5]	auto[0]	auto[0]	auto[0]	75	1			T1	2		T20	2		T62	4
all_values[5]	auto[0]	auto[0]	auto[1]	25	1			T18	1		T19	3		T20	1
all_values[5]	auto[0]	auto[1]	auto[0]	49	1			T1	1		T9	1		T18	1
all_values[5]	auto[0]	auto[1]	auto[1]	27	1			T9	1		T21	2		T63	1
all_values[5]	auto[1]	auto[0]	auto[1]	60	1			T1	1		T9	1		T18	2
all_values[5]	auto[1]	auto[1]	auto[1]	42	1			T1	3		T9	1		T19	2
all_values[6]	auto[0]	auto[0]	auto[0]	58	1			T1	2		T9	1		T18	3
all_values[6]	auto[0]	auto[0]	auto[1]	19	1			T1	1		T9	1		T62	1
all_values[6]	auto[0]	auto[1]	auto[0]	55	1			T1	1		T9	1		T19	2
all_values[6]	auto[0]	auto[1]	auto[1]	25	1			T57	2		T58	2		T59	1
all_values[6]	auto[1]	auto[0]	auto[1]	71	1			T1	3		T9	1		T18	1
all_values[6]	auto[1]	auto[1]	auto[1]	50	1			T20	1		T21	1		T57	2
all_values[7]	auto[0]	auto[0]	auto[0]	89	1			T1	1		T9	1		T18	1
all_values[7]	auto[0]	auto[1]	auto[0]	70	1			T1	2		T9	3		T18	1
all_values[7]	auto[1]	auto[0]	auto[1]	69	1			T1	1		T18	1		T19	1
all_values[7]	auto[1]	auto[1]	auto[1]	50	1			T1	3		T18	1		T19	1
all_values[8]	auto[0]	auto[0]	auto[0]	89	1			T1	4		T9	3		T18	1
all_values[8]	auto[0]	auto[1]	auto[0]	85	1			T1	3		T9	1		T18	1
all_values[8]	auto[1]	auto[0]	auto[1]	65	1			T18	1		T19	2		T20	1
all_values[8]	auto[1]	auto[1]	auto[1]	39	1			T18	1		T20	3		T62	1
all_values[9]	auto[0]	auto[0]	auto[0]	71	1			T1	3		T9	2		T18	2
all_values[9]	auto[0]	auto[0]	auto[1]	27	1			T19	1		T21	1		T56	2
all_values[9]	auto[0]	auto[1]	auto[0]	48	1			T1	1		T62	2		T63	1
all_values[9]	auto[0]	auto[1]	auto[1]	18	1			T19	2		T21	1		T64	1
all_values[9]	auto[1]	auto[0]	auto[1]	63	1			T1	3		T19	2		T20	3
all_values[9]	auto[1]	auto[1]	auto[1]	51	1			T9	2		T18	2		T19	1
all_values[10]	auto[0]	auto[0]	auto[0]	70	1			T9	2		T18	1		T20	3
all_values[10]	auto[0]	auto[0]	auto[1]	24	1			T18	1		T19	1		T57	1
all_values[10]	auto[0]	auto[1]	auto[0]	43	1			T19	1		T20	4		T62	1
all_values[10]	auto[0]	auto[1]	auto[1]	38	1			T1	2		T9	1		T19	2
all_values[10]	auto[1]	auto[0]	auto[1]	65	1			T1	4		T18	1		T19	1
all_values[10]	auto[1]	auto[1]	auto[1]	38	1			T1	1		T9	1		T18	1
all_values[11]	auto[0]	auto[0]	auto[0]	63	1			T1	2		T20	3		T21	2
all_values[11]	auto[0]	auto[0]	auto[1]	34	1			T9	2		T18	2		T19	2
all_values[11]	auto[0]	auto[1]	auto[0]	43	1			T1	1		T19	2		T56	1
all_values[11]	auto[0]	auto[1]	auto[1]	18	1			T19	1		T20	1		T21	1
all_values[11]	auto[1]	auto[0]	auto[1]	69	1			T1	3		T9	2		T18	2
all_values[11]	auto[1]	auto[1]	auto[1]	51	1			T1	1		T19	1		T20	2
all_values[12]	auto[0]	auto[0]	auto[0]	51	1			T1	2		T21	3		T62	2
all_values[12]	auto[0]	auto[0]	auto[1]	28	1			T9	2		T19	1		T63	1
all_values[12]	auto[0]	auto[1]	auto[0]	51	1			T1	4		T18	2		T20	3
all_values[12]	auto[0]	auto[1]	auto[1]	31	1			T9	1		T19	1		T20	1
all_values[12]	auto[1]	auto[0]	auto[1]	72	1			T1	1		T9	1		T20	3
all_values[12]	auto[1]	auto[1]	auto[1]	45	1			T18	2		T19	5		T56	1
all_values[13]	auto[0]	auto[0]	auto[0]	58	1			T1	2		T9	1		T18	1
all_values[13]	auto[0]	auto[0]	auto[1]	26	1			T18	1		T20	1		T21	3
all_values[13]	auto[0]	auto[1]	auto[0]	42	1			T1	1		T9	1		T20	2
all_values[13]	auto[0]	auto[1]	auto[1]	32	1			T20	1		T56	1		T63	1
all_values[13]	auto[1]	auto[0]	auto[1]	63	1			T1	3		T9	2		T18	1
all_values[13]	auto[1]	auto[1]	auto[1]	57	1			T1	1		T18	1		T20	1
all_values[14]	auto[0]	auto[0]	auto[0]	83	1			T1	3		T9	2		T19	4
all_values[14]	auto[0]	auto[0]	auto[1]	32	1			T1	1		T18	2		T21	1
all_values[14]	auto[0]	auto[1]	auto[0]	49	1			T1	1		T9	1		T19	1
all_values[14]	auto[0]	auto[1]	auto[1]	21	1			T20	1		T63	1		T57	3
all_values[14]	auto[1]	auto[0]	auto[1]	53	1			T1	1		T9	1		T18	2
all_values[14]	auto[1]	auto[1]	auto[1]	40	1			T1	1		T21	3		T63	1
all_values[15]	auto[0]	auto[0]	auto[0]	52	1			T1	1		T19	1		T20	3
all_values[15]	auto[0]	auto[0]	auto[1]	39	1			T9	1		T18	2		T19	1
all_values[15]	auto[0]	auto[1]	auto[0]	36	1			T1	5		T20	1		T57	3
all_values[15]	auto[0]	auto[1]	auto[1]	36	1			T9	1		T19	1		T21	1
all_values[15]	auto[1]	auto[0]	auto[1]	67	1			T19	3		T20	2		T21	2
all_values[15]	auto[1]	auto[1]	auto[1]	48	1			T1	1		T9	2		T18	2
all_values[16]	auto[0]	auto[0]	auto[0]	47	1			T9	1		T18	3		T21	2
all_values[16]	auto[0]	auto[0]	auto[1]	29	1			T1	1		T19	2		T20	1
all_values[16]	auto[0]	auto[1]	auto[0]	56	1			T1	1		T19	1		T20	2
all_values[16]	auto[0]	auto[1]	auto[1]	24	1			T1	1		T9	2		T56	1
all_values[16]	auto[1]	auto[0]	auto[1]	70	1			T1	3		T9	1		T19	1
all_values[16]	auto[1]	auto[1]	auto[1]	52	1			T1	1		T18	1		T19	3
all_values[17]	auto[0]	auto[0]	auto[0]	87	1			T1	1		T9	1		T18	4
all_values[17]	auto[0]	auto[1]	auto[0]	85	1			T1	3		T9	2		T19	3
all_values[17]	auto[1]	auto[0]	auto[1]	57	1			T1	2		T9	1		T20	2
all_values[17]	auto[1]	auto[1]	auto[1]	49	1			T1	1		T19	3		T21	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal