Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.15	97.53	93.65	94.55		100.00	100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	579277874	11213	0	0
ep_in_enable_rd_A	579277874	2658	0	0
ep_out_enable_rd_A	579277874	2508	0	0
in_iso_rd_A	579277874	2414	0	0
intr_enable_rd_A	579277874	3958	0	0
out_iso_rd_A	579277874	2352	0	0
phy_config_rd_A	579277874	1602	0	0
phy_pins_drive_rd_A	579277874	2266	0	0
rxenable_setup_rd_A	579277874	2752	0	0
set_nak_out_rd_A	579277874	2615	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579277874	11213	0	0
T229	27160	4	0	0
T230	36650	6	0	0
T231	8493	20	0	0
T246	10507	523	0	0
T247	6770	266	0	0
T252	3240	515	0	0
T254	27785	4	0	0
T255	4201	24	0	0
T256	6879	395	0	0
T263	4912	9	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579277874	2658	0	0
T248	4921	31	0	0
T254	27785	148	0	0
T289	19356	182	0	0
T300	8204	21	0	0
T303	15401	21	0	0
T316	70821	245	0	0
T317	24312	311	0	0
T318	8165	20	0	0
T319	55394	502	0	0
T320	9866	24	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579277874	2508	0	0
T248	4921	36	0	0
T254	27785	91	0	0
T300	8204	8	0	0
T303	15401	28	0	0
T316	70821	189	0	0
T317	24312	176	0	0
T318	8165	18	0	0
T319	55394	445	0	0
T321	5370	7	0	0
T322	4531	10	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579277874	2414	0	0
T248	4921	40	0	0
T254	27785	114	0	0
T300	8204	13	0	0
T303	15401	51	0	0
T316	70821	244	0	0
T317	24312	213	0	0
T318	8165	12	0	0
T319	55394	374	0	0
T321	5370	9	0	0
T322	4531	24	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579277874	3958	0	0
T237	2310	25	0	0
T248	4921	3	0	0
T254	27785	261	0	0
T300	8204	21	0	0
T303	15401	70	0	0
T316	70821	217	0	0
T317	24312	355	0	0
T323	4856	12	0	0
T324	4106	3	0	0
T325	2521	12	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579277874	2352	0	0
T248	4921	31	0	0
T254	27785	145	0	0
T300	8204	6	0	0
T303	15401	60	0	0
T316	70821	240	0	0
T317	24312	236	0	0
T318	8165	7	0	0
T319	55394	334	0	0
T321	5370	3	0	0
T322	4531	1	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579277874	1602	0	0
T248	4921	2	0	0
T254	27785	62	0	0
T261	6959	3	0	0
T300	8204	30	0	0
T303	15401	54	0	0
T316	70821	177	0	0
T317	24312	88	0	0
T319	55394	324	0	0
T321	5370	5	0	0
T326	5690	4	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579277874	2266	0	0
T248	4921	18	0	0
T254	27785	155	0	0
T300	8204	15	0	0
T303	15401	23	0	0
T316	70821	211	0	0
T317	24312	265	0	0
T318	8165	19	0	0
T319	55394	431	0	0
T321	5370	6	0	0
T322	4531	15	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579277874	2752	0	0
T248	4921	15	0	0
T254	27785	144	0	0
T300	8204	30	0	0
T303	15401	33	0	0
T316	70821	194	0	0
T317	24312	285	0	0
T318	8165	1	0	0
T319	55394	501	0	0
T320	9866	28	0	0
T321	5370	4	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	579277874	2615	0	0
T248	4921	13	0	0
T254	27785	145	0	0
T300	8204	47	0	0
T303	15401	54	0	0
T316	70821	245	0	0
T317	24312	229	0	0
T319	55394	560	0	0
T320	9866	25	0	0
T321	5370	12	0	0
T322	4531	11	0	0