Unified Coverage Report :: Module :: usbdev

Module : usbdev

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.03	97.53	88.06	94.55		100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	97.15	97.53	93.65	94.55		100.00	100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.15	97.53	93.65	94.55		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.86	98.11	95.94	97.44	93.22	98.30	98.17

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_event	100.00	100.00				100.00
gen_no_stubbed_memory.u_memory_1p	99.02	97.06				100.00	100.00
gen_no_stubbed_memory.u_tlul2sram	92.55	89.08	89.87			91.25	100.00
i_usbdev_iomux	80.83	100.00	73.33			100.00	50.00
intr_av_out_empty	86.94	90.00	77.78			80.00	100.00
intr_av_overflow	91.67	100.00	66.67			100.00	100.00
intr_av_setup_empty	86.94	90.00	77.78			80.00	100.00
intr_disconnected	93.75	100.00	75.00			100.00	100.00
intr_frame	89.58	100.00	58.33			100.00	100.00
intr_host_lost	93.75	100.00	75.00			100.00	100.00
intr_hw_pkt_received	86.94	90.00	77.78			80.00	100.00
intr_hw_pkt_sent	86.94	90.00	77.78			80.00	100.00
intr_link_in_err	89.58	100.00	58.33			100.00	100.00
intr_link_out_err	93.75	100.00	75.00			100.00	100.00
intr_link_reset	93.75	100.00	75.00			100.00	100.00
intr_link_resume	93.75	100.00	75.00			100.00	100.00
intr_link_suspend	89.58	100.00	58.33			100.00	100.00
intr_powered	89.58	100.00	58.33			100.00	100.00
intr_rx_bitstuff_err	93.75	100.00	75.00			100.00	100.00
intr_rx_crc_err	93.75	100.00	75.00			100.00	100.00
intr_rx_full	86.94	90.00	77.78			80.00	100.00
intr_rx_pid_err	93.75	100.00	75.00			100.00	100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_ctr_errors	65.57	84.21	50.00			62.50
u_ctr_in	54.65	78.95	25.00			60.00
u_ctr_nodata_in	66.96	84.21	50.00			66.67
u_ctr_out	54.65	78.95	25.00			60.00
u_reg	98.15	98.85	98.86	100.00		99.48	93.55
usbdev_avoutfifo	99.19	100.00	96.77			100.00	100.00
usbdev_avsetupfifo	99.19	100.00	96.77			100.00	100.00
usbdev_csr_assert	100.00						100.00
usbdev_impl	97.37	98.98	96.23		93.22	98.42	100.00
usbdev_rxfifo	99.22	100.00	96.88			100.00	100.00

Line Coverage for Module : usbdev

	Line No.	Total	Covered	Percent
TOTAL		162	158	97.53
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
ALWAYS	222	5	5	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	353	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	356	1	1	100.00
CONT_ASSIGN	360	1	0	0.00
ALWAYS	383	0	0
ALWAYS	383	3	3	100.00
ALWAYS	391	0	0
ALWAYS	391	4	4	100.00
ALWAYS	400	0	0
ALWAYS	400	3	3	100.00
ALWAYS	407	0	0
ALWAYS	407	3	3	100.00
ALWAYS	414	0	0
ALWAYS	414	3	3	100.00
ALWAYS	421	0	0
ALWAYS	421	2	2	100.00
ALWAYS	434	5	5	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	448	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
ALWAYS	464	3	3	100.00
ALWAYS	471	0	0
ALWAYS	471	3	3	100.00
ALWAYS	480	3	3	100.00
ALWAYS	492	3	3	100.00
ALWAYS	499	0	0
ALWAYS	499	3	3	100.00
ALWAYS	506	10	10	100.00
ALWAYS	525	3	3	100.00
ALWAYS	532	0	0
ALWAYS	532	3	3	100.00
ALWAYS	540	0	0
ALWAYS	540	3	3	100.00
ALWAYS	549	0	0
ALWAYS	549	3	3	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
CONT_ASSIGN	685	1	1	100.00
CONT_ASSIGN	687	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
ALWAYS	715	0	0
ALWAYS	715	8	8	100.00
CONT_ASSIGN	800	1	1	100.00
CONT_ASSIGN	801	1	1	100.00
CONT_ASSIGN	802	1	1	100.00
CONT_ASSIGN	803	1	1	100.00
CONT_ASSIGN	811	1	1	100.00
ALWAYS	820	8	8	100.00
CONT_ASSIGN	834	1	1	100.00
CONT_ASSIGN	835	0	0
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	897	1	1	100.00
CONT_ASSIGN	898	1	1	100.00
CONT_ASSIGN	902	1	1	100.00
CONT_ASSIGN	1165	1	1	100.00
CONT_ASSIGN	1166	1	1	100.00
CONT_ASSIGN	1167	1	1	100.00
CONT_ASSIGN	1168	1	1	100.00
CONT_ASSIGN	1208	1	1	100.00
CONT_ASSIGN	1211	1	1	100.00
CONT_ASSIGN	1220	1	1	100.00
ALWAYS	1223	5	5	100.00
ALWAYS	1232	3	3	100.00
CONT_ASSIGN	1245	1	1	100.00
CONT_ASSIGN	1248	1	1	100.00
CONT_ASSIGN	1255	1	1	100.00
ALWAYS	1259	3	3	100.00
CONT_ASSIGN	1266	1	1	100.00
CONT_ASSIGN	1271	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1283	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1297	1	0	0.00
CONT_ASSIGN	1301	1	0	0.00
CONT_ASSIGN	1304	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
123	1	1
167	1	1
220	1	1
222	1	1
223	1	1
225	1	1
226	1	1
228	1	1
257	1	1
258	1	1
259	1	1
263	1	1
264	1	1
266	1	1
268	1	1
316	1	1
321	1	1
324	1	1
327	1	1
352	1	1
353	1	1
354	1	1
355	1	1
356	1	1
360	0	1
383	1	1
384	1	1
385	1	1
391	1	1
392	1	1
393	1	1
394	1	1
400	1	1
401	1	1
402	1	1
407	1	1
408	1	1
409	1	1
414	1	1
415	1	1
416	1	1
421	1	1
422	1	1
434	1	1
435	1	1
436	1	1
438	1	1
439	1	1
442	1	1
443	1	1
447	1	1
448	1	1
449	1	1
451	1	1
456	1	1
457	1	1
458	1	1
460	1	1
464	1	1
465	1	1
466	1	1
			MISSING_ELSE
471	1	1
472	1	1
473	1	1
480	1	1
481	1	1
482	1	1
492	1	1
493	1	1
494	1	1
			MISSING_ELSE
499	1	1
500	1	1
501	1	1
506	1	1
507	1	1
508	1	1
509	1	1
510	1	1
512	1	1
514	1	1
515	1	1
516	1	1
518	1	1
			MISSING_ELSE
525	1	1
526	2	2
			MISSING_ELSE
532	1	1
533	1	1
534	1	1
540	1	1
541	1	1
542	1	1
549	1	1
550	1	1
551	1	1
559	1	1
560	1	1
561	1	1
684	1	1
685	1	1
687	1	1
688	1	1
706	1	1
709	1	1
715	1	1
716	1	1
717	1	1
718	1	1
719	1	1
720	1	1
722	1	1
723	1	1
800	1	1
801	1	1
802	1	1
803	1	1
811	1	1
820	1	1
821	1	1
822	1	1
823	1	1
825	1	1
826	1	1
828	1	1
829	1	1
			MISSING_ELSE
834	1	1
835		unreachable
838	1	1
839	1	1
897	1	1
898	1	1
902	1	1
1165	1	1
1166	1	1
1167	1	1
1168	1	1
1208	1	1
1211	1	1
1220	1	1
1223	1	1
1224	1	1
1225	1	1
1226	1	1
1227	1	1
			MISSING_ELSE
1232	1	1
1233	1	1
1235	1	1
1245	1	1
1248	1	1
1255	1	1
1259	1	1
1260	1	1
1262	1	1
1266	1	1
1271	1	1
1273	1	1
1281	1	1
1283	1	1
1285	1	1
1287	1	1
1297	0	1
1301	0	1
1304	0	1

---

Cond Coverage for Module : usbdev

	Total	Covered	Percent
Conditions	134	118	88.06
Logical	134	118	88.06
Non-Logical	0	0
Event	0	0

 LINE       167
 EXPRESSION (event_rx_crc5_err | event_rx_crc16_err)
             --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T124,T125,T72
1	0	Covered	T68,T69,T70

 LINE       220
 EXPRESSION (ns_cnt == 6'd47)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION (reg2hw.fifo_ctrl.avsetup_rst.qe & reg2hw.fifo_ctrl.avsetup_rst.q)
             ---------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T14,T15
1	0	Covered	T23,T91,T219
1	1	Covered	T3,T14,T15

 LINE       258
 EXPRESSION (reg2hw.fifo_ctrl.avout_rst.qe & reg2hw.fifo_ctrl.avout_rst.q)
             --------------1--------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T14,T15
1	0	Covered	T91,T219,T220
1	1	Covered	T3,T14,T15

 LINE       259
 EXPRESSION (reg2hw.fifo_ctrl.rx_rst.qe & reg2hw.fifo_ctrl.rx_rst.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T14,T15
1	0	Covered	T23,T91,T219
1	1	Covered	T3,T14,T15

 LINE       263
 EXPRESSION (connect_en & ((~avsetup_rvalid)))
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T14,T15
1	1	Covered	T1,T2,T3

 LINE       264
 EXPRESSION (connect_en & ((~avout_rvalid)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T14,T15
1	1	Covered	T1,T2,T3

 LINE       266
 EXPRESSION ((reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready))) | (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready))))
             --------------------------1-------------------------   ------------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T56,T58,T96
1	0	Covered	T57,T94

 LINE       266
 SUB-EXPRESSION (reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready)))
                 -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T14,T15
1	1	Covered	T57,T94

 LINE       266
 SUB-EXPRESSION (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready)))
                 ----------1----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T14,T15
1	1	Covered	T56,T58,T96

 LINE       268
 EXPRESSION (connect_en & ((~rx_fifo_rvalid)))
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       316
 EXPRESSION (reg2hw.rxfifo.ep.re | reg2hw.rxfifo.setup.re | reg2hw.rxfifo.size.re | reg2hw.rxfifo.buffer.re)
             ---------1---------   -----------2----------   ----------3----------   -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Not Covered
0	0	1	0	Not Covered
0	1	0	0	Not Covered
1	0	0	0	Not Covered

 LINE       327
 EXPRESSION (rx_wready & (rx_depth < 4'((RXFifoDepth - 1))))
             ----1----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T29,T112
1	1	Covered	T1,T2,T3

 LINE       442
 EXPRESSION (in_xact_starting ? in_buf[in_xact_start_ep] : in_buf_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       443
 EXPRESSION (in_xact_starting ? in_size[in_xact_start_ep] : in_size_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       447
 EXPRESSION (reg2hw.out_data_toggle.status.qe & reg2hw.out_data_toggle.mask.qe)
             ----------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T23,T26,T123

 LINE       456
 EXPRESSION (reg2hw.in_data_toggle.status.qe & reg2hw.in_data_toggle.mask.qe)
             ---------------1---------------   --------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T23,T26,T123

 LINE       465
 EXPRESSION (in_ep_xact_end && in_endpoint_val)
             -------1------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T4,T5

 LINE       493
 EXPRESSION (rx_wvalid && out_endpoint_val)
             ----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T4,T5

 LINE       512
 EXPRESSION (setup_received & out_endpoint_val)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T4,T5

 LINE       516
 EXPRESSION (in_ep_xact_end & in_endpoint_val)
             -------1------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T4,T5

 LINE       542
 EXPRESSION (reg2hw.configin[i].rdy.q | reg2hw.configin[i].pend.q)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T24,T27,T170
1	0	Covered	T3,T14,T15

 LINE       550
 EXPRESSION (set_sending[i] | set_sentbit[i] | update_pend[i])
             -------1------   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T3,T4,T5
1	0	0	Covered	T3,T4,T5

 LINE       551
 EXPRESSION (((~set_sentbit[i])) & ((~update_pend[i])))
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       560
 EXPRESSION (cfg_pinflip ? 1'b0 : usb_pullup_en)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T41,T88

 LINE       561
 EXPRESSION (((!cfg_pinflip)) ? 1'b0 : usb_pullup_en)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T41,T88
1	Covered	T1,T2,T3

 LINE       688
 EXPRESSION (reg2hw.usbctrl.resume_link_active.qe & reg2hw.usbctrl.resume_link_active.q)
             ------------------1-----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T101,T102,T103
1	0	Covered	T1,T2,T3
1	1	Covered	T101,T102,T103

 LINE       800
 EXPRESSION (usb_mem_b_req | sw_mem_a_req)
             ------1------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T23
1	0	Covered	T3,T4,T16

 LINE       801
 EXPRESSION (usb_mem_b_req ? usb_mem_b_write : sw_mem_a_write)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T16

 LINE       802
 EXPRESSION (usb_mem_b_req ? usb_mem_b_addr : sw_mem_a_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T16

 LINE       803
 EXPRESSION (usb_mem_b_req ? usb_mem_b_wdata : sw_mem_a_wdata)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T16

 LINE       826
 EXPRESSION (usb_mem_b_req & ((!usb_mem_b_write)))
             ------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16
1	1	Covered	T3,T4,T5

 LINE       834
 EXPRESSION (gen_no_stubbed_memory.mem_rvalid & ((!gen_no_stubbed_memory.mem_rsteering)))
             ----------------1---------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T23,T25,T26

 LINE       839
 EXPRESSION (gen_no_stubbed_memory.mem_b_read_q ? gen_no_stubbed_memory.mem_rdata : gen_no_stubbed_memory.mem_b_rdata_q)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       902
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T93,T221,T222
1	0	Covered	T1,T2,T3
1	1	Covered	T93,T221,T222

 LINE       1211
 EXPRESSION (use_diff_rcvr & ((~link_suspend)))
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       1220
 EXPRESSION (usb_rcvr_ok_counter_q == '0)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1224
 EXPRESSION (use_diff_rcvr & ((!usb_rx_enable_o)))
             ------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       1226
 EXPRESSION (us_tick && (usb_rcvr_ok_counter_q > '0))
             ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T223,T224,T225

 LINE       1248
 EXPRESSION (usb_ref_disable ? 1'b0 : event_sof)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T226,T227,T228

 LINE       1255
 EXPRESSION (usb_ref_pulse_o ? 1'b1 : ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q))
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T36,T37

 LINE       1255
 SUB-EXPRESSION ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q)
                 -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1255
 SUB-EXPRESSION (((!link_active)) || host_lost || usb_ref_disable)
                 --------1-------    ----2----    -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T226,T227,T228
0	1	0	Covered	T5,T27,T60
1	0	0	Covered	T1,T2,T3

 LINE       1271
 EXPRESSION (reg2hw.wake_control.suspend_req.qe & reg2hw.wake_control.suspend_req.q)
             -----------------1----------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       1273
 EXPRESSION (reg2hw.wake_control.wake_ack.qe & reg2hw.wake_control.wake_ack.q)
             ---------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       1310
 EXPRESSION (reg2hw.count_out.rst.qe & reg2hw.count_out.rst.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1336
 EXPRESSION (reg2hw.count_in.rst.qe & reg2hw.count_in.rst.q)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1359
 EXPRESSION (reg2hw.count_nodata_in.rst.qe & reg2hw.count_nodata_in.rst.q)
             --------------1--------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1376
 EXPRESSION (reg2hw.count_errors.rst.qe & reg2hw.count_errors.rst.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

---

Toggle Coverage for Module : usbdev

	Total	Covered	Percent
Totals	74	68	91.89
Total Bits	440	416	94.55
Total Bits 0->1	220	208	94.55
Total Bits 1->0	220	208	94.55

Ports	74	68	91.89
Port Bits	440	416	94.55
Port Bits 0->1	220	208	94.55
Port Bits 1->0	220	208	94.55

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T89,T34,T40	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T89,T34,T40	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T7,T68	Yes	T5,T7,T68	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T229,T230,T231	Yes	T229,T230,T231	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T89,T93,T221	Yes	T89,T93,T221	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T89,T93,T221	Yes	T89,T93,T221	OUTPUT
cio_usb_dp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_usb_dn_i	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
usb_rx_d_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_usb_dp_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cio_usb_dp_en_o	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	OUTPUT
cio_usb_dn_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cio_usb_dn_en_o	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	OUTPUT
usb_tx_se0_o	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	OUTPUT
usb_tx_d_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cio_sense_i	Yes	Yes	T1,T6,T7	Yes	T1,T2,T3	INPUT
usb_dp_pullup_o	Yes	Yes	T1,T2,T6	Yes	T1,T2,T3	OUTPUT
usb_dn_pullup_o	Yes	Yes	T1,T9,T232	Yes	T1,T41,T88	OUTPUT
usb_rx_enable_o	Yes	Yes	T1,T2,T6	Yes	T1,T2,T3	OUTPUT
usb_tx_use_d_se0_o	Yes	Yes	T40,T173,T216	Yes	T40,T69,T74	OUTPUT
usb_aon_suspend_req_o	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	OUTPUT
usb_aon_wake_ack_o	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	OUTPUT
usb_aon_bus_reset_i	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
usb_aon_sense_lost_i	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	INPUT
usb_aon_bus_not_idle_i	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
usb_aon_wake_detect_active_i	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
usb_ref_val_o	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
usb_ref_pulse_o	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
intr_pkt_received_o	Yes	Yes	T34,T40,T41	Yes	T34,T40,T41	OUTPUT
intr_pkt_sent_o	Yes	Yes	T35,T36,T42	Yes	T35,T36,T42	OUTPUT
intr_powered_o	Yes	Yes	T233,T234,T235	Yes	T233,T234,T235	OUTPUT
intr_disconnected_o	Yes	Yes	T37,T39,T59	Yes	T37,T39,T59	OUTPUT
intr_host_lost_o	Yes	Yes	T61,T233,T234	Yes	T61,T233,T234	OUTPUT
intr_link_reset_o	Yes	Yes	T62,T233,T234	Yes	T62,T233,T234	OUTPUT
intr_link_suspend_o	Yes	Yes	T234,T236,T237	Yes	T234,T236,T237	OUTPUT
intr_link_resume_o	Yes	Yes	T38,T63,T64	Yes	T38,T63,T64	OUTPUT
intr_av_out_empty_o	Yes	Yes	T43,T233,T235	Yes	T43,T233,T235	OUTPUT
intr_rx_full_o	Yes	Yes	T46,T50,T51	Yes	T46,T50,T51	OUTPUT
intr_av_overflow_o	Yes	Yes	T56,T57,T58	Yes	T56,T57,T58	OUTPUT
intr_link_in_err_o	Yes	Yes	T233,T238,T237	Yes	T233,T238,T237	OUTPUT
intr_link_out_err_o	Yes	Yes	T65,T66,T67	Yes	T65,T66,T67	OUTPUT
intr_rx_crc_err_o	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
intr_rx_pid_err_o	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
intr_rx_bitstuff_err_o	Yes	Yes	T68,T80,T81	Yes	T68,T80,T81	OUTPUT
intr_frame_o	Yes	Yes	T233,T235,T238	Yes	T233,T235,T238	OUTPUT
intr_av_setup_empty_o	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : usbdev

	Line No.	Total	Covered	Percent
Branches		48	48	100.00
TERNARY	442	2	2	100.00
TERNARY	443	2	2	100.00
TERNARY	560	2	2	100.00
TERNARY	561	2	2	100.00
TERNARY	1248	2	2	100.00
TERNARY	1255	3	3	100.00
TERNARY	801	2	2	100.00
TERNARY	802	2	2	100.00
TERNARY	803	2	2	100.00
TERNARY	839	2	2	100.00
IF	222	3	3	100.00
IF	434	2	2	100.00
IF	465	2	2	100.00
IF	493	2	2	100.00
IF	508	4	4	100.00
IF	526	2	2	100.00
IF	718	2	2	100.00
IF	1224	3	3	100.00
IF	1232	2	2	100.00
IF	1259	2	2	100.00
IF	820	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	442	(in_xact_starting) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	443	(in_xact_starting) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	560	(cfg_pinflip) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T41,T88
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	561	((!cfg_pinflip)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T41,T88

	LineNo.	Expression
-1-:	1248	(usb_ref_disable) ? 

Branches:

-1-	Status	Tests
1	Covered	T226,T227,T228
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1255	(usb_ref_pulse_o) ? 
-2-:	1255	((((!link_active) || host_lost) || usb_ref_disable)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T35,T36,T37
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	801	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	802	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	803	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	839	(gen_no_stubbed_memory.mem_b_read_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	if ((!rst_n))
-2-:	225	if (us_tick)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	434	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	465	if ((in_ep_xact_end && in_endpoint_val))

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	493	if ((rx_wvalid && out_endpoint_val))

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	508	if (event_link_reset)
-2-:	512	if ((setup_received & out_endpoint_val))
-3-:	516	if ((in_ep_xact_end & in_endpoint_val))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	526	if (in_xact_starting)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	718	if (((setup_received && out_endpoint_val) && (out_endpoint == 4'((unsigned'(i))))))

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1224	if ((use_diff_rcvr & (!usb_rx_enable_o)))
-2-:	1226	if ((us_tick && (usb_rcvr_ok_counter_q > '0)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T6
0	1	Covered	T223,T224,T225
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1232	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1259	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	820	if ((!rst_ni))
-2-:	828	if (gen_no_stubbed_memory.mem_b_read_q)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : usbdev

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	35	35	100.00	35	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	35	35	100.00	35	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	577485172	577200647	0	0
CIODnEnKnown_A	577485172	577200647	0	0
CIODnKnown_A	577485172	577200647	0	0
CIODpEnKnown_A	577485172	577200647	0	0
CIODpKnown_A	577485172	577200647	0	0
FpvSecCmRegWeOnehotCheck_A	577485172	60	0	0
TlOAReadyKnown_A	577485172	577200647	0	0
TlODValidKnown_A	577485172	577200647	0	0
USBAonSuspendReqKnown_A	577485172	577200647	0	0
USBAonWakeAckKnown_A	577485172	577200647	0	0
USBDnPUKnown_A	577485172	577200647	0	0
USBDpPUKnown_A	577485172	577200647	0	0
USBIntrAvOutEmptyKnown_A	577485172	577200647	0	0
USBIntrAvOverKnown_A	577485172	577200647	0	0
USBIntrAvSetupEmptyKnown_A	577485172	577200647	0	0
USBIntrDisConKnown_A	577485172	577200647	0	0
USBIntrFrameKnown_A	577485172	577200647	0	0
USBIntrHostLostKnown_A	577485172	577200647	0	0
USBIntrLinkInErrKnown_A	577485172	577200647	0	0
USBIntrLinkOutErrKnown_A	577485172	577200647	0	0
USBIntrLinkResKnown_A	577485172	577200647	0	0
USBIntrLinkRstKnown_A	577485172	577200647	0	0
USBIntrLinkSusKnown_A	577485172	577200647	0	0
USBIntrPktRcvdKnown_A	577485172	577200647	0	0
USBIntrPktSentKnown_A	577485172	577200647	0	0
USBIntrPwrdKnown_A	577485172	577200647	0	0
USBIntrRxBitstuffErrKnown_A	577485172	577200647	0	0
USBIntrRxCrCErrKnown_A	577485172	577200647	0	0
USBIntrRxFullKnown_A	577485172	577200647	0	0
USBIntrRxPidErrKnown_A	577485172	577200647	0	0
USBRefPulseKnown_A	577485172	577200647	0	0
USBRefValKnown_A	577485172	577200647	0	0
USBRxEnableKnown_A	577485172	577200647	0	0
USBTxDKnown_A	577485172	577200647	0	0
USBTxSe0Known_A	577485172	577200647	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

CIODnEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

CIODnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

CIODpEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

CIODpKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	60	0	0
T18	1715	0	0	0
T24	7223	0	0	0
T25	34780	0	0	0
T26	24109	0	0	0
T27	914112	0	0	0
T89	12332	10	0	0
T90	9159	0	0	0
T91	20904	0	0	0
T92	8389	0	0	0
T93	1764	0	0	0
T239	0	10	0	0
T240	0	10	0	0
T241	0	20	0	0
T242	0	10	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBAonSuspendReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBAonWakeAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBDnPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBDpPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrAvOutEmptyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrAvOverKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrAvSetupEmptyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrDisConKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrFrameKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrHostLostKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrLinkInErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrLinkOutErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrLinkResKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrLinkRstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrLinkSusKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrPktRcvdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrPktSentKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrPwrdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrRxBitstuffErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrRxCrCErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrRxFullKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrRxPidErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBRefPulseKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBRefValKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBRxEnableKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBTxDKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBTxSe0Known_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		162	158	97.53
CONT_ASSIGN	123	1	1	100.00
CONT_ASSIGN	167	1	1	100.00
CONT_ASSIGN	220	1	1	100.00
ALWAYS	222	5	5	100.00
CONT_ASSIGN	257	1	1	100.00
CONT_ASSIGN	258	1	1	100.00
CONT_ASSIGN	259	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	266	1	1	100.00
CONT_ASSIGN	268	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	324	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	353	1	1	100.00
CONT_ASSIGN	354	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	356	1	1	100.00
CONT_ASSIGN	360	1	0	0.00
ALWAYS	383	0	0
ALWAYS	383	3	3	100.00
ALWAYS	391	0	0
ALWAYS	391	4	4	100.00
ALWAYS	400	0	0
ALWAYS	400	3	3	100.00
ALWAYS	407	0	0
ALWAYS	407	3	3	100.00
ALWAYS	414	0	0
ALWAYS	414	3	3	100.00
ALWAYS	421	0	0
ALWAYS	421	2	2	100.00
ALWAYS	434	5	5	100.00
CONT_ASSIGN	442	1	1	100.00
CONT_ASSIGN	443	1	1	100.00
CONT_ASSIGN	447	1	1	100.00
CONT_ASSIGN	448	1	1	100.00
CONT_ASSIGN	449	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	456	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
ALWAYS	464	3	3	100.00
ALWAYS	471	0	0
ALWAYS	471	3	3	100.00
ALWAYS	480	3	3	100.00
ALWAYS	492	3	3	100.00
ALWAYS	499	0	0
ALWAYS	499	3	3	100.00
ALWAYS	506	10	10	100.00
ALWAYS	525	3	3	100.00
ALWAYS	532	0	0
ALWAYS	532	3	3	100.00
ALWAYS	540	0	0
ALWAYS	540	3	3	100.00
ALWAYS	549	0	0
ALWAYS	549	3	3	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	561	1	1	100.00
CONT_ASSIGN	684	1	1	100.00
CONT_ASSIGN	685	1	1	100.00
CONT_ASSIGN	687	1	1	100.00
CONT_ASSIGN	688	1	1	100.00
CONT_ASSIGN	706	1	1	100.00
CONT_ASSIGN	709	1	1	100.00
ALWAYS	715	0	0
ALWAYS	715	8	8	100.00
CONT_ASSIGN	800	1	1	100.00
CONT_ASSIGN	801	1	1	100.00
CONT_ASSIGN	802	1	1	100.00
CONT_ASSIGN	803	1	1	100.00
CONT_ASSIGN	811	1	1	100.00
ALWAYS	820	8	8	100.00
CONT_ASSIGN	834	1	1	100.00
CONT_ASSIGN	835	0	0
CONT_ASSIGN	838	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	897	1	1	100.00
CONT_ASSIGN	898	1	1	100.00
CONT_ASSIGN	902	1	1	100.00
CONT_ASSIGN	1165	1	1	100.00
CONT_ASSIGN	1166	1	1	100.00
CONT_ASSIGN	1167	1	1	100.00
CONT_ASSIGN	1168	1	1	100.00
CONT_ASSIGN	1208	1	1	100.00
CONT_ASSIGN	1211	1	1	100.00
CONT_ASSIGN	1220	1	1	100.00
ALWAYS	1223	5	5	100.00
ALWAYS	1232	3	3	100.00
CONT_ASSIGN	1245	1	1	100.00
CONT_ASSIGN	1248	1	1	100.00
CONT_ASSIGN	1255	1	1	100.00
ALWAYS	1259	3	3	100.00
CONT_ASSIGN	1266	1	1	100.00
CONT_ASSIGN	1271	1	1	100.00
CONT_ASSIGN	1273	1	1	100.00
CONT_ASSIGN	1281	1	1	100.00
CONT_ASSIGN	1283	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1297	1	0	0.00
CONT_ASSIGN	1301	1	0	0.00
CONT_ASSIGN	1304	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
123	1	1
167	1	1
220	1	1
222	1	1
223	1	1
225	1	1
226	1	1
228	1	1
257	1	1
258	1	1
259	1	1
263	1	1
264	1	1
266	1	1
268	1	1
316	1	1
321	1	1
324	1	1
327	1	1
352	1	1
353	1	1
354	1	1
355	1	1
356	1	1
360	0	1
383	1	1
384	1	1
385	1	1
391	1	1
392	1	1
393	1	1
394	1	1
400	1	1
401	1	1
402	1	1
407	1	1
408	1	1
409	1	1
414	1	1
415	1	1
416	1	1
421	1	1
422	1	1
434	1	1
435	1	1
436	1	1
438	1	1
439	1	1
442	1	1
443	1	1
447	1	1
448	1	1
449	1	1
451	1	1
456	1	1
457	1	1
458	1	1
460	1	1
464	1	1
465	1	1
466	1	1
			MISSING_ELSE
471	1	1
472	1	1
473	1	1
480	1	1
481	1	1
482	1	1
492	1	1
493	1	1
494	1	1
			MISSING_ELSE
499	1	1
500	1	1
501	1	1
506	1	1
507	1	1
508	1	1
509	1	1
510	1	1
512	1	1
514	1	1
515	1	1
516	1	1
518	1	1
			MISSING_ELSE
525	1	1
526	2	2
			MISSING_ELSE
532	1	1
533	1	1
534	1	1
540	1	1
541	1	1
542	1	1
549	1	1
550	1	1
551	1	1
559	1	1
560	1	1
561	1	1
684	1	1
685	1	1
687	1	1
688	1	1
706	1	1
709	1	1
715	1	1
716	1	1
717	1	1
718	1	1
719	1	1
720	1	1
722	1	1
723	1	1
800	1	1
801	1	1
802	1	1
803	1	1
811	1	1
820	1	1
821	1	1
822	1	1
823	1	1
825	1	1
826	1	1
828	1	1
829	1	1
			MISSING_ELSE
834	1	1
835		unreachable
838	1	1
839	1	1
897	1	1
898	1	1
902	1	1
1165	1	1
1166	1	1
1167	1	1
1168	1	1
1208	1	1
1211	1	1
1220	1	1
1223	1	1
1224	1	1
1225	1	1
1226	1	1
1227	1	1
			MISSING_ELSE
1232	1	1
1233	1	1
1235	1	1
1245	1	1
1248	1	1
1255	1	1
1259	1	1
1260	1	1
1262	1	1
1266	1	1
1271	1	1
1273	1	1
1281	1	1
1283	1	1
1285	1	1
1287	1	1
1297	0	1
1301	0	1
1304	0	1

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	126	118	93.65
Logical	126	118	93.65
Non-Logical	0	0
Event	0	0

 LINE       167
 EXPRESSION (event_rx_crc5_err | event_rx_crc16_err)
             --------1--------   ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T124,T125,T72
1	0	Covered	T68,T69,T70

 LINE       220
 EXPRESSION (ns_cnt == 6'd47)
            --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       257
 EXPRESSION (reg2hw.fifo_ctrl.avsetup_rst.qe & reg2hw.fifo_ctrl.avsetup_rst.q)
             ---------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T14,T15
1	0	Covered	T23,T91,T219
1	1	Covered	T3,T14,T15

 LINE       258
 EXPRESSION (reg2hw.fifo_ctrl.avout_rst.qe & reg2hw.fifo_ctrl.avout_rst.q)
             --------------1--------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T14,T15
1	0	Covered	T91,T219,T220
1	1	Covered	T3,T14,T15

 LINE       259
 EXPRESSION (reg2hw.fifo_ctrl.rx_rst.qe & reg2hw.fifo_ctrl.rx_rst.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T14,T15
1	0	Covered	T23,T91,T219
1	1	Covered	T3,T14,T15

 LINE       263
 EXPRESSION (connect_en & ((~avsetup_rvalid)))
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T14,T15
1	1	Covered	T1,T2,T3

 LINE       264
 EXPRESSION (connect_en & ((~avout_rvalid)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T14,T15
1	1	Covered	T1,T2,T3

 LINE       266
 EXPRESSION ((reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready))) | (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready))))
             --------------------------1-------------------------   ------------------------2-----------------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T56,T58,T96
1	0	Covered	T57,T94

 LINE       266
 SUB-EXPRESSION (reg2hw.avsetupbuffer.qe & ((~avsetup_fifo_wready)))
                 -----------1-----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T14,T15
1	1	Covered	T57,T94

 LINE       266
 SUB-EXPRESSION (reg2hw.avoutbuffer.qe & ((~avout_fifo_wready)))
                 ----------1----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T14,T15
1	1	Covered	T56,T58,T96

 LINE       268
 EXPRESSION (connect_en & ((~rx_fifo_rvalid)))
             -----1----   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T1,T2,T3

 LINE       316
 EXPRESSION (reg2hw.rxfifo.ep.re | reg2hw.rxfifo.setup.re | reg2hw.rxfifo.size.re | reg2hw.rxfifo.buffer.re)
             ---------1---------   -----------2----------   ----------3----------   -----------4-----------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Excluded		VC_COV_UNR
0	0	1	0	Excluded		VC_COV_UNR
0	1	0	0	Excluded		VC_COV_UNR
1	0	0	0	Excluded		VC_COV_UNR

 LINE       327
 EXPRESSION (rx_wready & (rx_depth < 4'((RXFifoDepth - 1))))
             ----1----   -----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T27,T29,T112
1	1	Covered	T1,T2,T3

 LINE       442
 EXPRESSION (in_xact_starting ? in_buf[in_xact_start_ep] : in_buf_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       443
 EXPRESSION (in_xact_starting ? in_size[in_xact_start_ep] : in_size_q)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       447
 EXPRESSION (reg2hw.out_data_toggle.status.qe & reg2hw.out_data_toggle.mask.qe)
             ----------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T23,T26,T123

 LINE       456
 EXPRESSION (reg2hw.in_data_toggle.status.qe & reg2hw.in_data_toggle.mask.qe)
             ---------------1---------------   --------------2--------------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Excluded		VC_COV_UNR
1	1	Covered	T23,T26,T123

 LINE       465
 EXPRESSION (in_ep_xact_end && in_endpoint_val)
             -------1------    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T4,T5

 LINE       493
 EXPRESSION (rx_wvalid && out_endpoint_val)
             ----1----    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T4,T5

 LINE       512
 EXPRESSION (setup_received & out_endpoint_val)
             -------1------   --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T4,T5

 LINE       516
 EXPRESSION (in_ep_xact_end & in_endpoint_val)
             -------1------   -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T3,T4,T5

 LINE       542
 EXPRESSION (reg2hw.configin[i].rdy.q | reg2hw.configin[i].pend.q)
             ------------1-----------   ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T24,T27,T170
1	0	Covered	T3,T14,T15

 LINE       550
 EXPRESSION (set_sending[i] | set_sentbit[i] | update_pend[i])
             -------1------   -------2------   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T3,T4,T5
1	0	0	Covered	T3,T4,T5

 LINE       551
 EXPRESSION (((~set_sentbit[i])) & ((~update_pend[i])))
             ---------1---------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T5
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       560
 EXPRESSION (cfg_pinflip ? 1'b0 : usb_pullup_en)
             -----1-----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T41,T88

 LINE       561
 EXPRESSION (((!cfg_pinflip)) ? 1'b0 : usb_pullup_en)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T41,T88
1	Covered	T1,T2,T3

 LINE       688
 EXPRESSION (reg2hw.usbctrl.resume_link_active.qe & reg2hw.usbctrl.resume_link_active.q)
             ------------------1-----------------   -----------------2-----------------

-1-	-2-	Status	Tests
0	1	Covered	T101,T102,T103
1	0	Covered	T1,T2,T3
1	1	Covered	T101,T102,T103

 LINE       800
 EXPRESSION (usb_mem_b_req | sw_mem_a_req)
             ------1------   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T23
1	0	Covered	T3,T4,T16

 LINE       801
 EXPRESSION (usb_mem_b_req ? usb_mem_b_write : sw_mem_a_write)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T16

 LINE       802
 EXPRESSION (usb_mem_b_req ? usb_mem_b_addr : sw_mem_a_addr)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T16

 LINE       803
 EXPRESSION (usb_mem_b_req ? usb_mem_b_wdata : sw_mem_a_wdata)
             ------1------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T16

 LINE       826
 EXPRESSION (usb_mem_b_req & ((!usb_mem_b_write)))
             ------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T16
1	1	Covered	T3,T4,T5

 LINE       834
 EXPRESSION (gen_no_stubbed_memory.mem_rvalid & ((!gen_no_stubbed_memory.mem_rsteering)))
             ----------------1---------------   --------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T4,T5
1	1	Covered	T23,T25,T26

 LINE       839
 EXPRESSION (gen_no_stubbed_memory.mem_b_read_q ? gen_no_stubbed_memory.mem_rdata : gen_no_stubbed_memory.mem_b_rdata_q)
             -----------------1----------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T4,T5

 LINE       902
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T93,T221,T222
1	0	Covered	T1,T2,T3
1	1	Covered	T93,T221,T222

 LINE       1211
 EXPRESSION (use_diff_rcvr & ((~link_suspend)))
             ------1------   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T3

 LINE       1220
 EXPRESSION (usb_rcvr_ok_counter_q == '0)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1224
 EXPRESSION (use_diff_rcvr & ((!usb_rx_enable_o)))
             ------1------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T6

 LINE       1226
 EXPRESSION (us_tick && (usb_rcvr_ok_counter_q > '0))
             ---1---    --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T223,T224,T225

 LINE       1248
 EXPRESSION (usb_ref_disable ? 1'b0 : event_sof)
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T226,T227,T228

 LINE       1255
 EXPRESSION (usb_ref_pulse_o ? 1'b1 : ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q))
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T35,T36,T37

 LINE       1255
 SUB-EXPRESSION ((((!link_active)) || host_lost || usb_ref_disable) ? 1'b0 : usb_ref_val_q)
                 -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1255
 SUB-EXPRESSION (((!link_active)) || host_lost || usb_ref_disable)
                 --------1-------    ----2----    -------3-------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T226,T227,T228
0	1	0	Covered	T5,T27,T60
1	0	0	Covered	T1,T2,T3

 LINE       1271
 EXPRESSION (reg2hw.wake_control.suspend_req.qe & reg2hw.wake_control.suspend_req.q)
             -----------------1----------------   ----------------2----------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       1273
 EXPRESSION (reg2hw.wake_control.wake_ack.qe & reg2hw.wake_control.wake_ack.q)
             ---------------1---------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T6
1	0	Covered	T1,T2,T6
1	1	Covered	T1,T2,T6

 LINE       1310
 EXPRESSION (reg2hw.count_out.rst.qe & reg2hw.count_out.rst.q)
             -----------1-----------   -----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1336
 EXPRESSION (reg2hw.count_in.rst.qe & reg2hw.count_in.rst.q)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1359
 EXPRESSION (reg2hw.count_nodata_in.rst.qe & reg2hw.count_nodata_in.rst.q)
             --------------1--------------   --------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       1376
 EXPRESSION (reg2hw.count_errors.rst.qe & reg2hw.count_errors.rst.q)
             -------------1------------   ------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	74	68	91.89
Total Bits	440	416	94.55
Total Bits 0->1	220	208	94.55
Total Bits 1->0	220	208	94.55

Ports	74	68	91.89
Port Bits	440	416	94.55
Port Bits 0->1	220	208	94.55
Port Bits 1->0	220	208	94.55

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T89,T34,T40	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T89,T34,T40	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T5,T7,T68	Yes	T5,T7,T68	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T229,T230,T231	Yes	T229,T230,T231	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T89,T93,T221	Yes	T89,T93,T221	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T89,T93,T221	Yes	T89,T93,T221	OUTPUT
cio_usb_dp_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_usb_dn_i	Yes	Yes	T3,T14,T15	Yes	T3,T14,T15	INPUT
usb_rx_d_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
cio_usb_dp_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cio_usb_dp_en_o	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	OUTPUT
cio_usb_dn_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cio_usb_dn_en_o	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	OUTPUT
usb_tx_se0_o	Yes	Yes	T3,T4,T16	Yes	T3,T4,T16	OUTPUT
usb_tx_d_o	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
cio_sense_i	Yes	Yes	T1,T6,T7	Yes	T1,T2,T3	INPUT
usb_dp_pullup_o	Yes	Yes	T1,T2,T6	Yes	T1,T2,T3	OUTPUT
usb_dn_pullup_o	Yes	Yes	T1,T9,T232	Yes	T1,T41,T88	OUTPUT
usb_rx_enable_o	Yes	Yes	T1,T2,T6	Yes	T1,T2,T3	OUTPUT
usb_tx_use_d_se0_o	Yes	Yes	T40,T173,T216	Yes	T40,T69,T74	OUTPUT
usb_aon_suspend_req_o	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	OUTPUT
usb_aon_wake_ack_o	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	OUTPUT
usb_aon_bus_reset_i	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
usb_aon_sense_lost_i	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	INPUT
usb_aon_bus_not_idle_i	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	INPUT
usb_aon_wake_detect_active_i	Yes	Yes	T1,T2,T6	Yes	T1,T2,T6	INPUT
usb_ref_val_o	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
usb_ref_pulse_o	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
ram_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.rf_cfg.test	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
ram_cfg_i.ram_cfg.test	No	No		No		INPUT
intr_pkt_received_o	Yes	Yes	T34,T40,T41	Yes	T34,T40,T41	OUTPUT
intr_pkt_sent_o	Yes	Yes	T35,T36,T42	Yes	T35,T36,T42	OUTPUT
intr_powered_o	Yes	Yes	T233,T234,T235	Yes	T233,T234,T235	OUTPUT
intr_disconnected_o	Yes	Yes	T37,T39,T59	Yes	T37,T39,T59	OUTPUT
intr_host_lost_o	Yes	Yes	T61,T233,T234	Yes	T61,T233,T234	OUTPUT
intr_link_reset_o	Yes	Yes	T62,T233,T234	Yes	T62,T233,T234	OUTPUT
intr_link_suspend_o	Yes	Yes	T234,T236,T237	Yes	T234,T236,T237	OUTPUT
intr_link_resume_o	Yes	Yes	T38,T63,T64	Yes	T38,T63,T64	OUTPUT
intr_av_out_empty_o	Yes	Yes	T43,T233,T235	Yes	T43,T233,T235	OUTPUT
intr_rx_full_o	Yes	Yes	T46,T50,T51	Yes	T46,T50,T51	OUTPUT
intr_av_overflow_o	Yes	Yes	T56,T57,T58	Yes	T56,T57,T58	OUTPUT
intr_link_in_err_o	Yes	Yes	T233,T238,T237	Yes	T233,T238,T237	OUTPUT
intr_link_out_err_o	Yes	Yes	T65,T66,T67	Yes	T65,T66,T67	OUTPUT
intr_rx_crc_err_o	Yes	Yes	T71,T72,T73	Yes	T71,T72,T73	OUTPUT
intr_rx_pid_err_o	Yes	Yes	T77,T78,T79	Yes	T77,T78,T79	OUTPUT
intr_rx_bitstuff_err_o	Yes	Yes	T68,T80,T81	Yes	T68,T80,T81	OUTPUT
intr_frame_o	Yes	Yes	T233,T235,T238	Yes	T233,T235,T238	OUTPUT
intr_av_setup_empty_o	Yes	Yes	T52,T53,T54	Yes	T52,T53,T54	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		48	48	100.00
TERNARY	442	2	2	100.00
TERNARY	443	2	2	100.00
TERNARY	560	2	2	100.00
TERNARY	561	2	2	100.00
TERNARY	1248	2	2	100.00
TERNARY	1255	3	3	100.00
TERNARY	801	2	2	100.00
TERNARY	802	2	2	100.00
TERNARY	803	2	2	100.00
TERNARY	839	2	2	100.00
IF	222	3	3	100.00
IF	434	2	2	100.00
IF	465	2	2	100.00
IF	493	2	2	100.00
IF	508	4	4	100.00
IF	526	2	2	100.00
IF	718	2	2	100.00
IF	1224	3	3	100.00
IF	1232	2	2	100.00
IF	1259	2	2	100.00
IF	820	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv' or '../src/lowrisc_ip_usbdev_0.1/rtl/usbdev.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	442	(in_xact_starting) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	443	(in_xact_starting) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	560	(cfg_pinflip) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T41,T88
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	561	((!cfg_pinflip)) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T41,T88

	LineNo.	Expression
-1-:	1248	(usb_ref_disable) ? 

Branches:

-1-	Status	Tests
1	Covered	T226,T227,T228
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1255	(usb_ref_pulse_o) ? 
-2-:	1255	((((!link_active) || host_lost) || usb_ref_disable)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T35,T36,T37
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	801	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	802	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	803	(usb_mem_b_req) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	839	(gen_no_stubbed_memory.mem_b_read_q) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	222	if ((!rst_n))
-2-:	225	if (us_tick)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	434	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	465	if ((in_ep_xact_end && in_endpoint_val))

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	493	if ((rx_wvalid && out_endpoint_val))

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	508	if (event_link_reset)
-2-:	512	if ((setup_received & out_endpoint_val))
-3-:	516	if ((in_ep_xact_end & in_endpoint_val))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T3,T4,T5
0	0	1	Covered	T3,T4,T5
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	526	if (in_xact_starting)

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	718	if (((setup_received && out_endpoint_val) && (out_endpoint == 4'((unsigned'(i))))))

Branches:

-1-	Status	Tests
1	Covered	T3,T4,T5
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1224	if ((use_diff_rcvr & (!usb_rx_enable_o)))
-2-:	1226	if ((us_tick && (usb_rcvr_ok_counter_q > '0)))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T6
0	1	Covered	T223,T224,T225
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1232	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	1259	if ((!rst_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	820	if ((!rst_ni))
-2-:	828	if (gen_no_stubbed_memory.mem_b_read_q)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T4,T5
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	35	35	100.00	35	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	35	35	100.00	35	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	577485172	577200647	0	0
CIODnEnKnown_A	577485172	577200647	0	0
CIODnKnown_A	577485172	577200647	0	0
CIODpEnKnown_A	577485172	577200647	0	0
CIODpKnown_A	577485172	577200647	0	0
FpvSecCmRegWeOnehotCheck_A	577485172	60	0	0
TlOAReadyKnown_A	577485172	577200647	0	0
TlODValidKnown_A	577485172	577200647	0	0
USBAonSuspendReqKnown_A	577485172	577200647	0	0
USBAonWakeAckKnown_A	577485172	577200647	0	0
USBDnPUKnown_A	577485172	577200647	0	0
USBDpPUKnown_A	577485172	577200647	0	0
USBIntrAvOutEmptyKnown_A	577485172	577200647	0	0
USBIntrAvOverKnown_A	577485172	577200647	0	0
USBIntrAvSetupEmptyKnown_A	577485172	577200647	0	0
USBIntrDisConKnown_A	577485172	577200647	0	0
USBIntrFrameKnown_A	577485172	577200647	0	0
USBIntrHostLostKnown_A	577485172	577200647	0	0
USBIntrLinkInErrKnown_A	577485172	577200647	0	0
USBIntrLinkOutErrKnown_A	577485172	577200647	0	0
USBIntrLinkResKnown_A	577485172	577200647	0	0
USBIntrLinkRstKnown_A	577485172	577200647	0	0
USBIntrLinkSusKnown_A	577485172	577200647	0	0
USBIntrPktRcvdKnown_A	577485172	577200647	0	0
USBIntrPktSentKnown_A	577485172	577200647	0	0
USBIntrPwrdKnown_A	577485172	577200647	0	0
USBIntrRxBitstuffErrKnown_A	577485172	577200647	0	0
USBIntrRxCrCErrKnown_A	577485172	577200647	0	0
USBIntrRxFullKnown_A	577485172	577200647	0	0
USBIntrRxPidErrKnown_A	577485172	577200647	0	0
USBRefPulseKnown_A	577485172	577200647	0	0
USBRefValKnown_A	577485172	577200647	0	0
USBRxEnableKnown_A	577485172	577200647	0	0
USBTxDKnown_A	577485172	577200647	0	0
USBTxSe0Known_A	577485172	577200647	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

CIODnEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

CIODnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

CIODpEnKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

CIODpKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	60	0	0
T18	1715	0	0	0
T24	7223	0	0	0
T25	34780	0	0	0
T26	24109	0	0	0
T27	914112	0	0	0
T89	12332	10	0	0
T90	9159	0	0	0
T91	20904	0	0	0
T92	8389	0	0	0
T93	1764	0	0	0
T239	0	10	0	0
T240	0	10	0	0
T241	0	20	0	0
T242	0	10	0	0

TlOAReadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

TlODValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBAonSuspendReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBAonWakeAckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBDnPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBDpPUKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrAvOutEmptyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrAvOverKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrAvSetupEmptyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrDisConKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrFrameKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrHostLostKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrLinkInErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrLinkOutErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrLinkResKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrLinkRstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrLinkSusKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrPktRcvdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrPktSentKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrPwrdKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrRxBitstuffErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrRxCrCErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrRxFullKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBIntrRxPidErrKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBRefPulseKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBRefValKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBRxEnableKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBTxDKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0

USBTxSe0Known_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	577485172	577200647	0	0
T1	723330	723255	0	0
T2	734495	734441	0	0
T3	92259	92199	0	0
T4	85419	85321	0	0
T5	280924	280831	0	0
T6	249022	248931	0	0
T14	8422	8357	0	0
T15	16878	16791	0	0
T16	7940	7841	0	0
T17	9847	9753	0	0