Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_usbdev_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	60967	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

62031

1

T1

44

T2

293

T3

400

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	74950	1			T1	224		T2	73		T3	244
values[0x0]	23605	1			T1	27		T2	120		T3	82
values[0x1]	24443	1			T1	24		T2	116		T3	74

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	42497	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

80501

1

T1

98

T2

305

T3

400

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	369	1			T1	3		T2	1		T8	2
valid_sources[0x01]	482	1			T1	3		T2	3		T3	1
valid_sources[0x02]	641	1			T2	1		T3	1		T8	1
valid_sources[0x03]	505	1			T2	2		T8	1		T7	1
valid_sources[0x04]	610	1			T2	2		T8	1		T18	3
valid_sources[0x05]	358	1			T2	6		T8	2		T15	1
valid_sources[0x06]	365	1			T2	3		T8	1		T32	1
valid_sources[0x07]	479	1			T2	1		T8	3		T4	12
valid_sources[0x08]	508	1			T2	2		T8	1		T19	1
valid_sources[0x09]	374	1			T1	3		T3	3		T4	8
valid_sources[0x0a]	639	1			T3	1		T4	2		T18	5
valid_sources[0x0b]	399	1			T8	2		T4	30		T33	1
valid_sources[0x0c]	448	1			T1	5		T3	1		T8	1
valid_sources[0x0d]	354	1			T1	1		T3	3		T8	1
valid_sources[0x0e]	361	1			T2	1		T8	1		T4	2
valid_sources[0x0f]	567	1			T3	1		T8	3		T19	2
valid_sources[0x10]	395	1			T1	5		T3	1		T7	1
valid_sources[0x11]	504	1			T3	1		T7	1		T16	1
valid_sources[0x12]	320	1			T2	1		T19	3		T32	1
valid_sources[0x13]	505	1			T3	3		T8	2		T15	2
valid_sources[0x14]	442	1			T3	3		T8	1		T19	1
valid_sources[0x15]	716	1			T2	4		T3	3		T4	17
valid_sources[0x16]	492	1			T3	2		T5	135		T18	19
valid_sources[0x17]	528	1			T2	4		T3	1		T8	3
valid_sources[0x18]	417	1			T2	2		T3	5		T5	59
valid_sources[0x19]	837	1			T2	1		T8	3		T5	216
valid_sources[0x1a]	637	1			T2	1		T3	2		T19	6
valid_sources[0x1b]	497	1			T3	11		T8	1		T19	7
valid_sources[0x1c]	390	1			T1	4		T2	2		T8	1
valid_sources[0x1d]	365	1			T1	2		T3	4		T19	1
valid_sources[0x1e]	435	1			T2	3		T3	7		T8	1
valid_sources[0x1f]	500	1			T2	2		T8	1		T4	5
valid_sources[0x20]	406	1			T2	2		T15	1		T5	55
valid_sources[0x21]	570	1			T2	1		T3	3		T8	1
valid_sources[0x22]	456	1			T2	2		T15	1		T19	1
valid_sources[0x23]	555	1			T2	1		T3	1		T19	5
valid_sources[0x24]	428	1			T3	5		T19	12		T14	4
valid_sources[0x25]	463	1			T3	3		T18	8		T19	2
valid_sources[0x26]	546	1			T3	1		T15	2		T34	2
valid_sources[0x27]	684	1			T2	1		T8	1		T5	75
valid_sources[0x28]	381	1			T2	1		T19	3		T32	1
valid_sources[0x29]	499	1			T2	3		T3	4		T8	3
valid_sources[0x2a]	493	1			T2	1		T8	2		T4	12
valid_sources[0x2b]	451	1			T2	1		T7	1		T19	2
valid_sources[0x2c]	455	1			T2	4		T3	13		T15	1
valid_sources[0x2d]	420	1			T1	3		T3	2		T8	2
valid_sources[0x2e]	666	1			T1	1		T2	2		T4	27
valid_sources[0x2f]	547	1			T2	1		T4	19		T5	82
valid_sources[0x30]	462	1			T2	2		T4	21		T19	10
valid_sources[0x31]	472	1			T2	1		T8	2		T7	1
valid_sources[0x32]	391	1			T3	3		T4	26		T15	3
valid_sources[0x33]	296	1			T2	3		T3	1		T4	10
valid_sources[0x34]	372	1			T2	1		T3	2		T8	1
valid_sources[0x35]	325	1			T1	1		T2	1		T15	1
valid_sources[0x36]	500	1			T2	2		T8	1		T31	1
valid_sources[0x37]	361	1			T18	13		T19	2		T31	1
valid_sources[0x38]	511	1			T1	1		T3	1		T8	1
valid_sources[0x39]	386	1			T32	1		T33	1		T34	26
valid_sources[0x3a]	445	1			T1	10		T8	2		T4	37
valid_sources[0x3b]	333	1			T2	3		T8	1		T4	25
valid_sources[0x3c]	536	1			T4	33		T19	5		T31	1
valid_sources[0x3d]	519	1			T2	1		T19	3		T14	10
valid_sources[0x3e]	433	1			T2	2		T3	2		T18	1
valid_sources[0x3f]	364	1			T1	2		T3	1		T8	1
valid_sources[0x40]	370	1			T2	3		T4	4		T18	5
valid_sources[0x41]	373	1			T3	1		T8	3		T19	2
valid_sources[0x42]	552	1			T2	1		T3	5		T4	18
valid_sources[0x43]	416	1			T2	1		T8	2		T19	2
valid_sources[0x44]	477	1			T8	1		T4	1		T18	13
valid_sources[0x45]	515	1			T32	1		T33	5		T34	4
valid_sources[0x46]	350	1			T1	1		T8	1		T7	1
valid_sources[0x47]	525	1			T2	2		T3	5		T8	1
valid_sources[0x48]	489	1			T2	1		T8	1		T4	43
valid_sources[0x49]	667	1			T2	2		T8	1		T31	3
valid_sources[0x4a]	576	1			T1	1		T2	1		T19	1
valid_sources[0x4b]	582	1			T2	1		T8	1		T19	1
valid_sources[0x4c]	369	1			T2	2		T8	1		T18	19
valid_sources[0x4d]	533	1			T2	2		T3	1		T8	2
valid_sources[0x4e]	403	1			T2	1		T3	1		T8	2
valid_sources[0x4f]	535	1			T2	1		T4	5		T19	2
valid_sources[0x50]	403	1			T2	1		T8	1		T15	1
valid_sources[0x51]	408	1			T2	1		T3	1		T8	1
valid_sources[0x52]	359	1			T3	3		T32	1		T33	2
valid_sources[0x53]	361	1			T7	1		T31	1		T26	8
valid_sources[0x54]	443	1			T1	5		T2	2		T3	3
valid_sources[0x55]	486	1			T2	2		T3	5		T8	3
valid_sources[0x56]	417	1			T2	1		T8	1		T7	1
valid_sources[0x57]	464	1			T2	2		T5	73		T19	1
valid_sources[0x58]	759	1			T2	2		T8	2		T5	287
valid_sources[0x59]	585	1			T2	2		T8	1		T19	1
valid_sources[0x5a]	456	1			T2	2		T8	1		T19	12
valid_sources[0x5b]	1971	1			T8	3		T31	2		T32	1
valid_sources[0x5c]	340	1			T8	1		T19	6		T32	2
valid_sources[0x5d]	418	1			T2	1		T8	1		T4	6
valid_sources[0x5e]	651	1			T1	2		T2	2		T4	24
valid_sources[0x5f]	493	1			T2	2		T3	4		T8	1
valid_sources[0x60]	420	1			T1	4		T2	1		T6	40
valid_sources[0x61]	1623	1			T3	6		T4	17		T5	186
valid_sources[0x62]	464	1			T2	1		T3	3		T8	2
valid_sources[0x63]	741	1			T18	16		T31	4		T32	1
valid_sources[0x64]	617	1			T1	1		T2	1		T3	2
valid_sources[0x65]	496	1			T2	2		T3	1		T32	1
valid_sources[0x66]	479	1			T3	1		T8	1		T19	2
valid_sources[0x67]	389	1			T3	2		T19	1		T31	2
valid_sources[0x68]	362	1			T2	3		T8	1		T16	1
valid_sources[0x69]	474	1			T3	4		T8	1		T4	18
valid_sources[0x6a]	373	1			T2	1		T8	2		T6	33
valid_sources[0x6b]	350	1			T2	1		T8	1		T32	3
valid_sources[0x6c]	448	1			T1	2		T8	1		T32	1
valid_sources[0x6d]	463	1			T1	10		T2	2		T8	1
valid_sources[0x6e]	615	1			T2	1		T7	1		T4	2
valid_sources[0x6f]	307	1			T1	1		T2	2		T3	1
valid_sources[0x70]	517	1			T2	1		T3	4		T8	4
valid_sources[0x71]	433	1			T8	1		T18	8		T19	1
valid_sources[0x72]	634	1			T1	4		T3	4		T7	1
valid_sources[0x73]	447	1			T2	1		T3	3		T4	23
valid_sources[0x74]	490	1			T2	1		T3	5		T8	1
valid_sources[0x75]	789	1			T2	1		T3	8		T8	3
valid_sources[0x76]	424	1			T2	3		T3	1		T19	6
valid_sources[0x77]	777	1			T8	1		T4	7		T5	77
valid_sources[0x78]	524	1			T1	4		T2	2		T3	4
valid_sources[0x79]	371	1			T1	3		T2	2		T3	3
valid_sources[0x7a]	620	1			T1	1		T2	1		T15	1
valid_sources[0x7b]	345	1			T1	2		T2	1		T3	1
valid_sources[0x7c]	378	1			T5	24		T18	8		T19	7
valid_sources[0x7d]	379	1			T2	1		T8	1		T4	7
valid_sources[0x7e]	539	1			T8	2		T7	1		T19	1
valid_sources[0x7f]	490	1			T3	5		T8	1		T19	1
valid_sources[0x80]	425	1			T2	1		T3	2		T19	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

24974

1

T1

16

T2

69

T3

244

values[0x0]

all_enables

biggest_size

19764

1

T1

18

T2

120

T3

82

values[0x1]

all_enables

biggest_size

17293

1

T1

10

T2

104

T3

74