Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[usbdev_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

74402

1

T1

231

T2

204

T8

178

full_word

62885

1

T1

44

T2

300

T3

400

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	136997	1			T1	275		T2	504		T3	400
auto[TlIntgErrCmd]	94	1			T5	4		T26	4		T27	4
auto[TlIntgErrData]	102	1			T5	7		T26	2		T27	8
auto[TlIntgErrBoth]	94	1			T5	9		T26	4		T27	8

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

76533

1

T1

224

T2

87

T3

244

auto[1]

60754

1

T1

51

T2

417

T3

156

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	51250	1			T1	208		T2	17		T8	160
auto[TlIntgErrNone]	partial	auto[1]	22881	1			T1	23		T2	187		T8	18
auto[TlIntgErrNone]	full_word	auto[0]	25150	1			T1	16		T2	70		T3	244
auto[TlIntgErrNone]	full_word	auto[1]	37716	1			T1	28		T2	230		T3	156
auto[TlIntgErrCmd]	partial	auto[0]	37	1			T5	2		T26	1		T27	1
auto[TlIntgErrCmd]	partial	auto[1]	48	1			T5	1		T26	2		T27	2
auto[TlIntgErrCmd]	full_word	auto[0]	4	1			T27	1		T30	1		T61	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1			T5	1		T26	1		T30	1
auto[TlIntgErrData]	partial	auto[0]	49	1			T5	4		T27	3		T30	1
auto[TlIntgErrData]	partial	auto[1]	48	1			T5	3		T26	2		T27	4
auto[TlIntgErrData]	full_word	auto[0]	1	1			T27	1		-	-		-	-
auto[TlIntgErrData]	full_word	auto[1]	4	1			T48	1		T62	1		T63	1
auto[TlIntgErrBoth]	partial	auto[0]	39	1			T5	4		T26	3		T27	3
auto[TlIntgErrBoth]	partial	auto[1]	50	1			T5	5		T26	1		T27	5
auto[TlIntgErrBoth]	full_word	auto[0]	3	1			T48	1		T64	1		T65	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1			T29	1		T66	1		-	-