Unified Coverage Report :: Module :: usbdev_csr_assert_fpv

Module : usbdev_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_usbdev_csr_assert_0/usbdev_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.usbdev_csr_assert	100.00						100.00

---

Module Instance : tb.dut.usbdev_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
22.73	0.00	0.00	90.91		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : usbdev_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	10	10	100.00	10	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	10	10	100.00	10	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1714146	11078	0	0
ep_in_enable_rd_A	1714146	3222	0	0
ep_out_enable_rd_A	1714146	3378	0	0
in_iso_rd_A	1714146	3431	0	0
intr_enable_rd_A	1714146	4150	0	0
out_iso_rd_A	1714146	3259	0	0
phy_config_rd_A	1714146	1944	0	0
phy_pins_drive_rd_A	1714146	2687	0	0
rxenable_setup_rd_A	1714146	3583	0	0
set_nak_out_rd_A	1714146	3157	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714146	11078	0	0
T2	5161	259	0	0
T3	7619	0	0	0
T4	4644	18	0	0
T5	65173	8	0	0
T6	0	19	0	0
T7	2049	0	0	0
T8	2903	0	0	0
T14	4499	0	0	0
T15	1726	0	0	0
T18	10588	0	0	0
T19	12619	684	0	0
T20	0	596	0	0
T21	0	766	0	0
T26	0	4	0	0
T27	0	2	0	0
T29	0	3	0	0

ep_in_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714146	3222	0	0
T1	4145	35	0	0
T2	5161	0	0	0
T3	7619	0	0	0
T4	4644	0	0	0
T5	65173	0	0	0
T7	2049	0	0	0
T8	2903	0	0	0
T15	1726	0	0	0
T18	10588	3	0	0
T19	12619	0	0	0
T27	0	351	0	0
T37	0	8	0	0
T38	0	37	0	0
T40	0	278	0	0
T50	0	256	0	0
T51	0	136	0	0
T52	0	15	0	0
T53	0	443	0	0

ep_out_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714146	3378	0	0
T1	4145	72	0	0
T2	5161	0	0	0
T3	7619	0	0	0
T4	4644	0	0	0
T5	65173	0	0	0
T7	2049	0	0	0
T8	2903	0	0	0
T15	1726	0	0	0
T18	10588	1	0	0
T19	12619	7	0	0
T27	0	562	0	0
T37	0	10	0	0
T38	0	6	0	0
T50	0	191	0	0
T51	0	92	0	0
T52	0	4	0	0
T53	0	506	0	0

in_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714146	3431	0	0
T1	4145	79	0	0
T2	5161	0	0	0
T3	7619	0	0	0
T4	4644	0	0	0
T5	65173	0	0	0
T7	2049	0	0	0
T8	2903	0	0	0
T15	1726	0	0	0
T18	10588	31	0	0
T19	12619	0	0	0
T27	0	527	0	0
T37	0	1	0	0
T38	0	30	0	0
T40	0	250	0	0
T50	0	206	0	0
T51	0	83	0	0
T52	0	62	0	0
T53	0	628	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714146	4150	0	0
T1	4145	91	0	0
T2	5161	0	0	0
T3	7619	0	0	0
T4	4644	0	0	0
T5	65173	0	0	0
T7	2049	0	0	0
T8	2903	0	0	0
T15	1726	0	0	0
T17	0	12	0	0
T18	10588	48	0	0
T19	12619	0	0	0
T27	0	798	0	0
T42	0	9	0	0
T50	0	239	0	0
T51	0	86	0	0
T54	0	7	0	0
T55	0	8	0	0
T56	0	34	0	0

out_iso_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714146	3259	0	0
T1	4145	58	0	0
T2	5161	0	0	0
T3	7619	0	0	0
T4	4644	0	0	0
T5	65173	0	0	0
T7	2049	0	0	0
T8	2903	0	0	0
T15	1726	0	0	0
T18	10588	16	0	0
T19	12619	0	0	0
T27	0	573	0	0
T37	0	6	0	0
T38	0	26	0	0
T40	0	245	0	0
T50	0	188	0	0
T51	0	112	0	0
T52	0	3	0	0
T53	0	409	0	0

phy_config_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714146	1944	0	0
T1	4145	11	0	0
T2	5161	0	0	0
T3	7619	0	0	0
T4	4644	0	0	0
T5	65173	0	0	0
T7	2049	0	0	0
T8	2903	0	0	0
T15	1726	0	0	0
T18	10588	16	0	0
T19	12619	4	0	0
T27	0	265	0	0
T37	0	6	0	0
T38	0	6	0	0
T50	0	140	0	0
T51	0	82	0	0
T52	0	6	0	0
T53	0	312	0	0

phy_pins_drive_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714146	2687	0	0
T1	4145	32	0	0
T2	5161	0	0	0
T3	7619	0	0	0
T4	4644	0	0	0
T5	65173	0	0	0
T7	2049	0	0	0
T8	2903	0	0	0
T15	1726	0	0	0
T18	10588	16	0	0
T19	12619	0	0	0
T27	0	324	0	0
T37	0	36	0	0
T38	0	3	0	0
T40	0	230	0	0
T50	0	254	0	0
T51	0	101	0	0
T52	0	11	0	0
T53	0	491	0	0

rxenable_setup_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714146	3583	0	0
T1	4145	97	0	0
T2	5161	0	0	0
T3	7619	0	0	0
T4	4644	0	0	0
T5	65173	0	0	0
T7	2049	0	0	0
T8	2903	0	0	0
T15	1726	0	0	0
T18	10588	0	0	0
T19	12619	0	0	0
T27	0	564	0	0
T37	0	37	0	0
T38	0	32	0	0
T40	0	192	0	0
T50	0	348	0	0
T51	0	128	0	0
T52	0	51	0	0
T53	0	752	0	0
T57	0	1	0	0

set_nak_out_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1714146	3157	0	0
T1	4145	43	0	0
T2	5161	0	0	0
T3	7619	0	0	0
T4	4644	0	0	0
T5	65173	0	0	0
T7	2049	0	0	0
T8	2903	0	0	0
T15	1726	0	0	0
T18	10588	21	0	0
T19	12619	0	0	0
T27	0	582	0	0
T37	0	39	0	0
T38	0	2	0	0
T40	0	218	0	0
T50	0	136	0	0
T51	0	106	0	0
T52	0	13	0	0
T53	0	425	0	0